SBAS649B June   2021  – June 2022 DAC12DL3200

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Power Consumption
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 2xRF Mode
      2. 7.3.2 DAC Output Interface
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-scale Current Adjustment
        3. 7.3.2.3 Example Analog Output Interfaces
      3. 7.3.3 LVDS Interface
        1. 7.3.3.1 MODE0: Two LVDS banks per channel
        2. 7.3.3.2 MODE1: One LVDS bank per channel
        3. 7.3.3.3 MODE2: Four LVDS banks, single channel mode
        4. 7.3.3.4 LVDS Interface Input Strobe
        5. 7.3.3.5 FIFO Operation
          1. 7.3.3.5.1 Using FIFO Delay Readback Values
          2. 7.3.3.5.2 FIFO Delay Handling
          3. 7.3.3.5.3 FIFO Delay and NCO Operation
          4. 7.3.3.5.4 FIFO Over/Under Flow Alarming
      4. 7.3.4 Multi-Device Synchronization (SYSREF+/-)
        1. 7.3.4.1 DACCLK Domain Synchronization
        2. 7.3.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      5. 7.3.5 Alarms
    4. 7.4 Device Functional Modes
      1. 7.4.1 Direct Digital Synthesis (DDS) Mode
        1. 7.4.1.1 NCO Gain Scaling
        2. 7.4.1.2 NCO Phase Continuous Operation
        3. 7.4.1.3 Trigger Clock
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Operation
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 SPI Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure with LVDS Input
      2. 8.1.2 Startup Procedure With NCO Operation
      3. 8.1.3 Interface Test Pattern and Timing Verification
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2 SPI Register Map

Table 7-10 lists the SPI registers. All register addresses not listed in Table 7-10 should be considered as reserved locations and the register contents should not be modified. Reserved fields should be written to their default settings. Multi-byte registers are always in little-endian format (least significant byte stored at the lowest address).

The different register types are listed in Table 7-9.

Table 7-9 Register Types
Type Description
R Read Only
R/W Read and Write
W1C Write 1 to Clear
Table 7-10 SPI Registers
AddressAcronymRegister NameSection
0hCONFIG_AConfiguration A Go
2hDEVICE_CONFIGDevice Configuration Go
3hCHIP_TYPEChip Type Go
4hCHIP_IDChip Identification Go
6hCHIP_VERSIONChip Version Go
ChVENDOR_IDVendor Identification Go
20hPIN_CFGPin Configuration Go
21hTXEN_SELTransmitter Enable Control Selection Go
22hTXENTransmitter Enable Configuration Go
3ChIO_STATECurrent State of Input IOs Go
48hDCM_ENDual Clock Mode Go
50hTRIG_DIVTrigger Clock Divide Go
51hTRIG_OUT_ENTrigger Clock Output Enable Go
80hSYSREF_CTRLSYSREF Control Go
90hSYSREF_POSSYSREF Capture Position Go
100hDP_ENDatapath Enable Go
101hCH_CFGChannel Configuration Go
106hLVDS_CFGLSB Strobe Control Go
107hLVDS_TERMLVDS Termination Configuration Go
140hDITH_ENDAC Dither Enable Go
160hMXMODEDAC Output Mode Go
170hCOARSE_CURCoarse Current Control (DAC A and B) Go
171hCUR_ACurrent Control for DAC A Go
172hCUR_BCurrent Control for DAC B Go
180hSPIDAC_CHG_BLKSPIDAC Change Block Go
181hSPIDAC_VALUESample Value for SPIDAC Mode Go
1A0hSHUNTREF-ENEnable Shunt RegulatorsGo
200hFIFO_DLYFIFO Delay Go
210hFIFO_DLY_R0Current FIFO Delay for FIFO0 Go
211hFIFO_DLY_R1Current FIFO Delay for FIFO1 Go
212hFIFO_DLY_R2Current FIFO Delay for FIFO2 Go
213hFIFO_DLY_R3Current FIFO Delay for FIFO3 Go
220hFIFO_ALIGNFIFO Alignment Control Go
300hNCO_SYNCNCO Sync Source Select Go
301hNCO_SPISELNCO Fast-Frequency Hopping Frequency Selection Go
303hNCO_BANKCFGNCO Bank Configuration Go
308hNCO_ENNCO Enable Go
310hSPI_SYNCSPI Sync Go
320hNCO_CHG_BLKNCO Change Blocking Go
330hNCO_RAMPRATENCO Ramp Rate Control Go
331hNCO_CONFIGNCO Ramp Rate Control Go
332hNCO_GAIN_AGain Backoff for NCO A Go
334hNCO_GAIN_BGain Backoff for NCO B Go
400hFFH_FREQ_A[15:0]Frequency Word for Fast-Frequency Hopping Go
440hFFH_FREQ_B[15:0]Frequency Word for Fast-Frequency Hopping Go
480hFFH_PHASE_A[15:0]Phase Word for Fast-Frequency Hopping Go
4A0hFFH_PHASE_B[15:0] Phase Word for Fast-Frequency Hopping Go
700hTS_TEMPTemperature Reading in Celsius Go
701hTS_SLEEPTemperature Sensor Sleep Go
710hIOTEST_CFGIOTEST Configuration Go
711hIOTEST_CTRLIOTEST Control Go
712hIOTEST_SUMIOTEST Status Go
720hIOTEST_PAT[7:0]IOTEST Pattern Memory Go
750hIOTEST_STAT0IOTEST Bank0 Failure Status Go
752hIOTEST_STAT1IOTEST Bank1 Failure Status Go
754hIOTEST_STAT2IOTEST Bank2 Failure Status Go
756hIOTEST_STAT3IOTEST Bank3 Failure Status Go
760hIOTEST_CAP0[7:0]IOTEST Bank0 Capture Memory Go
770hIOTEST_CAP1[7:0]IOTEST Bank1 Capture Memory Go
780hIOTEST_CAP2[7:0]IOTEST Bank2 Capture Memory Go
790hIOTEST_CAP3[7:0]IOTEST Bank3 Capture Memory Go
800hSYNC_STATUSSynchronization Status Go
820hFIFO_ALMFIFO Alarm Status Go
821hLVDS_ALMLVDS Strobe Alarm Go
822hSYS_ALMSystem Alarm Status Go
823hALM_MASKAlarm Mask Go
824hMUTE_MASKDAC Mute Mask Go
900h FUSE_STATUS Fuse Status Go
B02h SYSREF_PS_EN SYSREF Windowing Persistence Enable Go

7.5.2.1 CONFIG_A Register (Address = 0h) [reset = 30h]

CONFIG_A is shown in Figure 7-25 and described in Table 7-11.

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Configuration A (default: 0x30)

Figure 7-25 CONFIG_A Register
76543210
SOFT_RESETRESERVEDASCENDRESERVEDRESERVED
R/W-0hR/W-0hR/W-1hR/W-1hR/W-0h
Table 7-11 CONFIG_A Register Field Descriptions
BitFieldTypeResetDescription
7SOFT_RESETR/W0hWriting a 1 to this bit causes a full reset of the chip and all SPI registers (including CONFIG_A). This bit is self-clearing and will always read zero. After writing this bit, the part may take up to 5 ns to reset. During this time, do not perform any SPI transactions.
6RESERVEDR/W0h
5ASCENDR/W1h0 : Address is decremented during streaming reads/writes
1 : Address is incremented during streaming reads/writes (default)
4RESERVEDR1hAlways read 1.
3-0RESERVEDR/W0h

7.5.2.2 DEVICE_CONFIG Register (Address = 2h) [reset = 00h]

DEVICE_CONFIG is shown in Figure 7-26 and described in Table 7-12.

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Device Configuration (default: 0x00)

Figure 7-26 DEVICE_CONFIG Register
76543210
RESERVEDMODE
R/W-0hR/W-0h
Table 7-12 DEVICE_CONFIG Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R/W 0h
1-0 MODE R/W 0h 0 : Normal operation (default)
1 : Full operation with reduced power/performance (not supported).
2 : Sleep operation (low power, fast resume). This will sleep both DACs, clock receiver, bandgap, LVDS receivers, and temp sensor.
3 : Full power down (lowest power, slowest resume).

7.5.2.3 CHIP_TYPE Register (Address = 3h) [reset = 04h]

CHIP_TYPE is shown in Figure 7-27 and described in Table 7-13.

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Chip Type (read-only: 0x04)

Figure 7-27 CHIP_TYPE Register
76543210
RESERVEDCHIP_TYPE
R/W-0hR-4h
Table 7-13 CHIP_TYPE Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3-0CHIP_TYPER4hAlways returns 0x4, indicating that the part is a high speed DAC.

7.5.2.4 CHIP_ID Register (Address = 4h) [reset = 3Ah]

CHIP_ID is shown in Figure 7-28 and described in Table 7-14.

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Chip Identification (read-only)

Figure 7-28 CHIP_ID Register
15141312111098
CHIP_ID
R-0h
76543210
CHIP_ID
R-3Ah
Table 7-14 CHIP_ID Register Field Descriptions
BitFieldTypeResetDescription
15-0CHIP_IDR003Ah Always returns 3A, indicating it is a DAC12DL3200

7.5.2.5 CHIP_VERSION Register (Address = 6h) [reset = 2h]

CHIP_VERSION is shown in Figure 7-29 and described in Table 7-15.

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Chip Version (read-only)

Figure 7-29 CHIP_VERSION Register
76543210
CHIP_VERSION
R-2h
Table 7-15 CHIP_VERSION Register Field Descriptions
BitFieldTypeResetDescription
7-0CHIP_VERSIONR2h

7.5.2.6 VENDOR_ID Register (Address = Ch) [reset = 0451h]

VENDOR_ID is shown in Figure 7-30 and described in Table 7-16.

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Vendor Identification (default: 0x0451)

Figure 7-30 VENDOR_ID Register
15141312111098
VENDOR_ID
R-451h
76543210
VENDOR_ID
R-451h
Table 7-16 VENDOR_ID Register Field Descriptions
BitFieldTypeResetDescription
15-0VENDOR_IDR451h

7.5.2.7 PIN_CFG Register (Address = 20h) [reset = 00h]

PIN_CFG is shown in Figure 7-31 and described in Table 7-17.

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Pin Configuration (default: 0x00)

Figure 7-31 PIN_CFG Register
76543210
RESERVEDSLEEP_CFG
R/W-0hR/W-0h
Table 7-17 PIN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0SLEEP_CFGR/W0hSet the behavior of the sleep input (SLEEP pin on part):
0: Asserting the pin is equivalent to setting MODE = 2
1: Asserting the pin is equivalent to setting MODE = 3

Note: Asserting the sleep input only affects the behavior of the part, not the value in the MODE register.

7.5.2.8 TXEN_SEL Register (Address = 21h) [reset = 0Fh]

TXEN_SEL is shown in Figure 7-32 and described in Table 7-18.

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Transmitter Enable Control Selection (default: 0x0F)

Figure 7-32 TXEN_SEL Register
76543210
RESERVEDAUTOMUTE_BAUTOMUTE_AUSE_TXEN_B USE_TXEN_A
R/W-0hR/W-1hR/W-1hR/W-1hR/W-1h
Table 7-18 TXEN_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR/W0h
3AUTOMUTE_BR/W1hWhen set, DACB is automatically muted by alarms whose mute mask is not set. When cleared, DACB is not automatically muted by any alarms.
2AUTOMUTE_AR/W1hWhen set, DACA is automatically muted by alarms whose mute mask is not set. When cleared, DACA is not automatically muted by any alarms.
1USE_TXEN_BR/W1h

0: DACB is controlled by the txenable input (TXENABLE pin on part). In this mode, TXEN_B is ignored.

1: DACB is controlled by TXEN_B. In this mode the txenable input does not affect DACB.

0USE_TXEN_AR/W1h

[0] USE_TXEN_A
0: DACA is controlled by the txenable input (TXENABLE pin on part). In this mode, TXEN_A is ignored.

1: DACA is controlled by TXEN_A. In this mode the txenable input does not affect DACA.

7.5.2.9 TXEN Register (Address = 22h) [reset = 00h]

TXEN is shown in Figure 7-33 and described in Table 7-19.

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Transmitter Enable Configuration (default: 0x00)

Figure 7-33 TXEN Register
76543210
RESERVEDTXEN_BTXEN_A
R/W-0hR/W-0hR/W-0h
Table 7-19 TXEN Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0h
1TXEN_BR/W0hWhen USE_TXEN_B = 1, this bit controls the transmitter enable for DACB.
0TXEN_AR/W0hWhen USE_TXEN_A = 1, this bit controls the transmitter enable for DACA.

7.5.2.10 IO_STATE Register (Address = 3Ch) [reset = 0h]

IO_STATE is shown in Figure 7-34 and described in Table 7-20.

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Current State of Input IOs (read-only)

Figure 7-34 IO_STATE Register
76543210
SLEEP_INSYNCB_INTXENABLE_INNCO_BANKSEL_INNCO_SEL_IN
R-0hR-0hR-0hR-0hR-0h
Table 7-20 IO_STATE Register Field Descriptions
BitFieldTypeResetDescription
7SLEEP_INR0hReturns the current state of the sleep input.
6SYNCB_INR0hReturns the current state of the sync_n input.
5TXENABLE_INR0hReturns the current state of the txenable input.
4NCO_BANKSEL_INR0hReturns the sampled value on nco_banksel at the last rising edge of trig_c. This value will not update if DEVCLK is not running.
3-0NCO_SEL_INR0hReturns the sampled value on nco_sel at the last rising edge of trig_c. This value will not update if DEVCLK is not running.

7.5.2.11 DCM_EN Register (Address = 48h) [reset = 0h]

DCM_EN is shown in Figure 7-35 and described in Table 7-21.

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Dual Clock Mode (default:0x00)

Figure 7-35 DCM_EN Register
76543210
RESERVEDDCM_EN
R/W-0hR/W-0h
Table 7-21 DCM_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0DCM_ENR/W0h0: Single Clock Mode (SCM) – DAC puts out each sample for one clock
1: Dual Clock Mode (DCM) – DAC puts out each sample for two clocks

Note: This register should only be changed when DP_EN=0

Note: Enabling transmission while DCM_EN=1 && LVDS_MODE=2 will result in undefined behavior. Enabling transmission while DCM_EN=0 && (MXMODE_A=3 || MXMODE_B=3) will result in undefined behavior.

7.5.2.12 TRIG_DIV Register (Address = 50h) [reset = 0h]

TRIG_DIV is shown in Figure 7-36 and described in Table 7-22.

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Trigger Clock Divide (default: 0x7F)

Figure 7-36 TRIG_DIV Register
76543210
RESERVEDTRIG_DIV
R/W-0hR/W-0h
Table 7-22 TRIG_DIV Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0h
6-0TRIG_DIVR/W0hFTRIGCLK = FDEVCLK / 8 /(DCM_EN+1)/ (TRIG_DIV+1)
Note: TRIG_DIV should be programmed to keep the output clock <100MHz.

Note: This register should only be changed when NCO_EN=0

7.5.2.13 TRIG_OUT_EN Register (Address = 51h) [reset = 00h]

TRIG_OUT_EN is shown in Figure 7-37 and described in Table 7-23.

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Trigger Clock Output Enable (default: 0x00)

Figure 7-37 TRIG_OUT_EN Register
76543210
RESERVEDTRIG_OUT_EN
R/W-0hR/W-0h
Table 7-23 TRIG_OUT_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0TRIG_OUT_ENR/W0h0: trig_clk output is driven low
1: The trigger clock (trig_c) is driven on the trig_clk output whenever NCO_EN is high.

7.5.2.14 SYSREF_CTRL Register (Address = 80h) [reset = 002000h]

SYSREF_CTRL is shown in Figure 7-38 and described in Table 7-24.

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SYSREF Control (default: 0x200000)

Figure 7-38 SYSREF_CTRL Register
15 14 13 12 11 10 9 8
SYSREF_PROC_ENRESERVEDSYSREF_RECV_SLEEPRESERVEDSYSREF_POS_SEL
R/W-0hR/W-0hR/W-1hR-0hR/W-0h
7 6 5 4 3 2 1 0
RESERVEDSYSREF_ZOOMSYSREF_SEL
R-0hR/W-0hR/W-0h
Table 7-24 SYSREF_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15SYSREF_PROC_ENR/W0hWhen set, this bit enables the SYSREF processor. When this is enabled, the system receives and processes each new SYSREF edge. User should always clear SYSREF_RECV_SLEEP before setting this bit. This bit is provided to allow the SYSREF receiver to stabilize before allowing the SYSREF to come to the digital.
14RESERVEDR/W0h
13SYSREF_RECV_SLEEPR/W1hClear this bit to enable the SYSREF receiver circuit. User should always clear SYSREF_PROC_EN before setting this bit.
12-9RESERVEDR0h
8SYSREF_POS_SELR/W0hAlways write 0.
7-6RESERVEDR0h
4SYSREF_ZOOMR/W0hSet this bit to “zoom” in the SYSREF strobe status (impacts SYSREF_POS and the step size of SYSREF_SEL).
3-0SYSREF_SELR/W0hSet this field to select which SYSREF delay to use. Set this based on the results returned by SYSREF_POS.

7.5.2.15 SYSREF_POS Register (Address = 90h) [reset = 0h]

SYSREF_POS is shown in Figure 7-39 and described in Table 7-25.

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SYSREF Capture Position (read-only)

Figure 7-39 SYSREF_POS Register
15141312111098
SYSREF_POS
R-0h
76543210
SYSREF_POS
R-0h
Table 7-25 SYSREF_POS Register Field Descriptions
BitFieldTypeResetDescription
15-0SYSREF_POSR0h

Returns a 16-bit status value that indicates the position of the SYSREF edge with respect to DEVCLK. Use this to determine the proper programming for SYSREF_SEL and SYSREF_ZOOM.

For CHIP_VERSION=2, this register can report either an accumulation of all the SYSREF edges seen since SYSREF_PS_EN transitioned from 0 to 1 (infinite persistence) or just the last SYSREF edge (when SYSREF_PS_EN=0). The user should reset the persistence after changing SYSREF_POS_SEL

7.5.2.16 DP_EN Register (Address = 100h) [reset = 00h]

DP_EN is shown in Figure 7-40 and described in Table 7-26.

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Datapath Enable (default: 0x00)

Figure 7-40 DP_EN Register
76543210
RESERVEDDP_EN
R/W-0hR/W-0h
Table 7-26 DP_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0DP_ENR/W0hSetting this bit enables datapath operation. When cleared, the datapath is held in reset. This bit should be set after the chip is configured for proper operation.

Note: This register should only be changed from 0 to 1 when FUSE_DONE=1 and NCO_EN=0.

7.5.2.17 CH_CFG Register (Address = 101h) [reset = 02h]

CH_CFG is shown in Figure 7-41 and described in Table 7-27.

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Channel Configuration (default: 0x02).

Note: This register should only be changed when DP_EN=0.

Note: When neither DAC is using LVDS as the source, LVDS_MODE and DCM_EN are still used to determine the max DACCLK rate. See Table 7-3. Note: Enabling transmission while LVDS_MODE=2 && DCM_EN=1 will result in undefined behavior.

Figure 7-41 CH_CFG Register
76543210
DACB_SRCDACA_SRCRESERVEDLVDS_MODE
R/W-0hR/W-0hR/W-0hR/W-2h
Table 7-27 CH_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6DACB_SRCR/W0h0: Disable (DACB powered down)

1: LVDS

2: NCO

3: SPIDAC

5-4DACA_SRCR/W0h

0: Disable (DACA powered down)

1: LVDS

2: NCO

3: SPIDAC

3-2RESERVEDR/W0h
1-0LVDS_MODER/W2h

0: 1 bank per DAC

1: 2 banks per DAC

2: 4 banks per DAC

3: RESERVED

7.5.2.18 LVDS_CFG Register (Address = 106h) [reset = 00h]

LVDS_CFG is shown in Figure 7-42 and described in Table 7-28.

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LSB Strobe Control (default: 0x00)

Figure 7-42 LVDS_CFG Register
76543210
RESERVEDLVDS_RESOLUTIONRESERVEDLSB_SYNC
R/W-0hR/W-0hR/W-0hR/W-0h
Table 7-28 LVDS_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0h
6-4LVDS_RESOLUTIONR/W0hThe value of LVDS_RESOLUTION will determine the operating resolution according to the following table:
0: 12-bit input mode
1: 11-bit input mode
2: 10-bit input mode
3: 9-bit input mode
>3: 8-bit input mode
3-1RESERVEDR/W0h
0LSB_SYNCR/W0hWhen set, this bit causes the LSB of the LVDS data to be used as SYNC regardless of the state of the sync_n input.

7.5.2.19 LVDS_TERM Register (Address = 107h) [reset = 01h]

LVDS_TERM is shown in Figure 7-43 and described in Table 7-29.

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LVDS Termination Configuration (default: 0x01)

Figure 7-43 LVDS_TERM Register
76543210
RESERVEDLVDS_TERM
R/W-0hR/W-1h
Table 7-29 LVDS_TERM Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0LVDS_TERMR/W1hWhen set, this bit causes the LVDS inputs to be differentially terminated with 100 Ohms. If this bit isn’t set there is no termination resistance between the pairs.

7.5.2.20 DITH_EN Register (Address = 140h) [reset = 00h]

DITH_EN is shown in Figure 7-44 and described in Table 7-30.

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DAC Dither Enable (default: 0x00).

Note: Changes to this register may only be made while TXENABLE (ball or register) for the channels being reconfigured is low.

Figure 7-44 DITH_EN Register
7 6 5 4 3 2 1 0
RESERVED DITH_EN_B DITH_EN_A
R/W-0h R/W-0h R/W-0h
Table 7-30 DITH_EN Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R/W 0h
3-2 DITH_EN_B R/W 0h

0: Dither Disabled

1: Use +1 to -2 LSBs of dither

2: Use +3 to -4 LSBs of dither

3: Use +7 to -8 LSBs of dither
1-0 DITH_EN_A R/W 0h

0: Dither Disabled

1: Use +1 to -2 LSBs of dither

2: Use +3 to -4 LSBs of dither

3: Use +7 to -8 LSBs of dither

7.5.2.21 MXMODE Register (Address = 160h) [reset = 00h]

MXMODE is shown in Figure 7-45 and described in Table 7-31.

Note: This register should only be changed when DP_EN=0.

Note: Enabling transmission while DCM_EN=0 && (MXMODE_A=3 || MXMODE_B=3) will result in undefined behavior.

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DAC Pulse Mode (default: 0x00)

Figure 7-45 MXMODE Register
76543210
RESERVEDMXMODE_BRESERVEDMXMODE_A
R/W-0hR/W-0hR/W-0hR/W-0h
Table 7-31 MXMODE Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0h
5-4MXMODE_BR/W0hSpecify the DAC pulse format for DACB.
0 : Normal mode (non-return-to-zero) (sinc nulls at n*FS)
1 : Mixed Mode (return to inverse) (sinc nulls at DC and 2n*FS)
2 : Return-to-Zero (RTZ) (sinc nulls at 2n*FS)
3 : 2XRF Mode (zero, signal, inverse, zero) – requires DCM_EN=1
3-2RESERVEDR/W0h
1-0MXMODE_AR/W0hSpecify the DAC pulse format for DACA.
0 : Normal mode (non-return-to-zero) (sinc nulls at n*FS)
1 : Mixed Mode (return to inverse) (sinc nulls at DC and 2n*FS)
2 : Return-to-Zero (RTZ) (sinc nulls at 2n*FS)
3 : 2XRF Mode (zero, signal, inverse, zero) – requires DCM_EN=1

7.5.2.22 COARSE_CUR Register (Address = 170h) [reset = 00h]

COARSE_CUR is shown in Figure 7-46 and described in Table 7-32.

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Coarse Current Control (DAC A and B) (default: 0x00)

Figure 7-46 COARSE_CUR Register
76543210
COARSE_CUR_BCOARSE_CUR_A
R/W-0hR/W-0h
Table 7-32 COARSE_CUR Register Field Descriptions
BitFieldTypeResetDescription
7-4COARSE_CUR_BR/W0hCoarse current control for DAC B.
3-0COARSE_CUR_AR/W0hCoarse current control for DAC A.

7.5.2.23 CUR_A Register (Address = 171h) [reset = 9Fh]

CUR_A is shown in Figure 7-47 and described in Table 7-33.

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Current Control for DAC A (default: 0x9f)

Figure 7-47 CUR_A Register
76543210
CUR_EN_ARESERVEDFINE_CUR_A
R/W-1hR/W-0hR/W-1Fh
Table 7-33 CUR_A Register Field Descriptions
BitFieldTypeResetDescription
7CUR_EN_AR/W1hCurrent enable for DAC A. If this is disabled, user needs to pulldown their DAC output bias to avoid reliability concerns. Disabling this causes the DAC to lose its DC operating point and will take some time to recover when it is turned on.
6RESERVEDR/W0h
5-0FINE_CUR_AR/W1FhFine current control for DAC A.

7.5.2.24 CUR_B Register (Address = 172h) [reset = 9Fh]

CUR_B is shown in Figure 7-48 and described in Table 7-34.

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Current Control for DAC B (default: 0x9f)

Figure 7-48 CUR_B Register
76543210
CUR_EN_BRESERVEDFINE_CUR_B
R/W-1hR/W-0hR/W-1Fh
Table 7-34 CUR_B Register Field Descriptions
BitFieldTypeResetDescription
7CUR_EN_BR/W1hCurrent enable for DAC B. If this is disabled, user needs to pulldown their DAC output bias to avoid reliability concerns. Disabling this causes the DAC to lose its DC operating point and will take some time to recover when it is turned on.
6RESERVEDR/W0h
5-0FINE_CUR_BR/W1FhFine current control for DAC B.

7.5.2.25 SPIDAC_CHG_BLK Register (Address = 180h) [reset = 00h]

SPIDAC_CHG_BLK is shown in Figure 7-49 and described in Table 7-35.

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SPIDAC Change Block (default: 0x00)

Figure 7-49 SPIDAC_CHG_BLK Register
76543210
RESERVEDSPIDAC_CHG_BLK
R/W-0hR/W-0h
Table 7-35 SPIDAC_CHG_BLK Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0SPIDAC_CHG_BLKR/W0hWhen set, changes to the SPIDAC_VALUE are not propagated to the high speed clocks and any DAC configured to use the SPIDAC continues to use its current value. When cleared, the SPIDAC_VALUE is used by the DAC’s. The user must set this before changing SPIDAC_VALUE if DP_EN=1.

7.5.2.26 SPIDAC_VALUE Register (Address = 181h) [reset = 0000h]

SPIDAC_VALUE is shown in Figure 7-50 and described in Table 7-36.

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Sample value for SPIDAC Mode (default: 0x0000)

Figure 7-50 SPIDAC_VALUE Register
15141312111098
SPIDAC_VALUE
R/W-0h
76543210
SPIDAC_VALUE
R/W-0h
Table 7-36 SPIDAC_VALUE Register Field Descriptions
BitFieldTypeResetDescription
15-0SPIDAC_VALUER/W0hThis field defines the constant sample value fed to a DAC configured to use the SPIDAC. Changes to this register are synchronously applied to both DACs. See DACA_SRC and DACB_SRC. This value should only be changed when DP_EN=0 or SPIDAC_CHG_BLK=1.

Note: Changes to the value can only propagate to the DAC output when SPIDAC_CHG_BLK is clear.

7.5.2.27 SHUNTREG_EN Register (Address = 1A0h-1A1h) [reset = 0000h]

SHUNTREG_EN is shown in Figure 7-51 and described in Table 7-37.

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Enable Shunt Regulators (default: 0x0000). Recommended setting used in device characterization is 0x0FFF.

Figure 7-51 SHUNTREG_EN Register
15141312111098
SHUNTREG_CLKDIST_ENSHUNTREG_CLKGEN_ENSHUNTREG_SYSREF_ENRESERVEDSHUNTREG_MUX_DACB_ENSHUNTREG_SWDRV_DACB_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
SHUNTREG_CLKDRV_DACB_ENSHUNTREG_MUX_DACA_ENSHUNTREG_SWDRV_DACA_ENSHUNTREG_CLKDRV_DACA_EN
R/W-0hR/W-0hR/W-0hR/W-0h
Table 7-37 SHUNTREG_EN Register Field Descriptions
BitFieldTypeResetDescription
15SHUNTREG_CLKDIST_ENR/W0h Enable shunt regulators on SYSREF receiver.
14SHUNTREG_CLKGEN_ENR/W0hEnable shunt regulators on clock distribution supply.
SHUNTREG_SYSREF_ENR/W0hEnable shunt regulators on SYSREF receiver.
12RESERVEDR/W0hReserved.
11:10SHUNTREG_MUX_DACB_ENR/W0hEnable shunt regulators on the DACB MUX supplies.
9:8SHUNTREG_SWDRV_DACB_ENR/W0hEnable shunt regulators on the DACB Switch Driver supplies.
7:6SHUNTREG_CLKDRV_DACB_ENR/W0hEnable shunt regulators on the DACB Clock Driver supplies.
5:4SHUNTREG_MUX_DACA_ENR/W0hEnable shunt regulators on the DACA MUX supplies.
3:2SHUNTREG_SWDRV_DACA_ENR/W0hEnable shunt regulators on the DACA Switch Driver supplies.
1:0SHUNTREG_CLKDRV_DACA_ENR/W0hEnable shunt regulators on the DACA Clock Driver supplies.

7.5.2.28 FIFO_DLY Register (Address = 200h) [reset = 0h]

FIFO_DLY is shown in Figure 7-52 and described in Table 7-38.

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FIFO Delay (default: 0x08)

Figure 7-52 FIFO_DLY Register
76543210
RESERVEDFIFO_DLY
R/W-0hR/W-0h
Table 7-38 FIFO_DLY Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR/W0h
4-0FIFO_DLYR/W0hThis sets the number of DAC clocks after the effective SYSREF edge before the first samples are expected to be available at the back of the FIFO.

Note: Changes to this register should only be made while TXENABLE is low for both DACs.

Note: This register should only be changed when NCO_EN=0. This register does affect the NCO alignment with respect to SYSREF. See Section 7.3.3.5.3.

7.5.2.29 FIFO_DLY_R0 Register (Address = 210h) [reset = 0h]

FIFO_DLY_R0 is shown in Figure 7-53 and described in Table 7-39.

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Current FIFO Delay for FIFO0 (read-only)

Figure 7-53 FIFO_DLY_R0 Register
76543210
RESERVEDFIFO_DLY_R0
R-0hR-0h
Table 7-39 FIFO_DLY_R0 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h
4-0FIFO_DLY_R0R0hThis reports the approximate setting for FIFO_DLY that would result in sample being used just as it arrives under current conditions. (This is the approximate number of DAC clocks after the effective SYSREF edge when the first sample is available at the back of the FIFO.)

7.5.2.30 FIFO_DLY_R1 Register (Address = 211h) [reset = 0h]

FIFO_DLY_R1 is shown in Figure 7-54 and described in Table 7-40.

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Current FIFO Delay for FIFO1 (read-only)

Figure 7-54 FIFO_DLY_R1 Register
76543210
RESERVEDFIFO_DLY_R1
R-0hR-0h
Table 7-40 FIFO_DLY_R1 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h
4-0FIFO_DLY_R1R0hThis reports the approximate setting for FIFO_DLY that would result in sample being used just as it arrives under current conditions. (This is the approximate number of DAC clocks after the effective SYSREF edge when the first sample is available at the back of the FIFO minus 1.)

7.5.2.31 FIFO_DLY_R2 Register (Address = 212h) [reset = 0h]

FIFO_DLY_R2 is shown in Figure 7-55 and described in Table 7-41.

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Current FIFO Delay for FIFO2 (read-only)

Figure 7-55 FIFO_DLY_R2 Register
76543210
RESERVEDFIFO_DLY_R2
R-0hR-0h
Table 7-41 FIFO_DLY_R2 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h
4-0FIFO_DLY_R2R0hThis reports the approximate setting for FIFO_DLY that would result in sample being used just as it arrives under current conditions. (This is the approximate number of DAC clocks after the effective SYSREF edge when the first sample is available at the back of the FIFO minus 2 for LVDS_MODE==0 and minus 0 otherwise.)

7.5.2.32 FIFO_DLY_R3 Register (Address = 213h) [reset = 0h]

FIFO_DLY_R3 is shown in Figure 7-56 and described in Table 7-42.

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Current FIFO Delay for FIFO3 (read-only)

Figure 7-56 FIFO_DLY_R3 Register
76543210
RESERVEDFIFO_DLY_R3
R-0hR-0h
Table 7-42 FIFO_DLY_R3 Register Field Descriptions
BitFieldTypeResetDescription
7-5RESERVEDR0h
4-0FIFO_DLY_R3R0hThis reports the approximate setting for FIFO_DLY that would result in sample being used just as it arrives under current conditions. (This is the approximate number of DAC clocks after the effective SYSREF edge when the first sample is available at the back of the FIFO minus 3 for LVDS_MODE==0 and minus 1 otherwise.)

7.5.2.33 FIFO_ALIGN Register (Address = 220h) [reset = 0h]

FIFO_ALIGN is shown in Figure 7-57 and described in Table 7-43.

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FIFO Alignment Control (default: 0x00)

Figure 7-57 FIFO_ALIGN Register
76543210
RESERVEDLVDS_STROBE_ALIGNSYSREF_ALIGN_EN
R/W-0hR/W-0hR/W-0h
Table 7-43 FIFO_ALIGN Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0h
1LVDS_STROBE_ALIGNR/W0hWriting ‘1’ to this register when it is ‘0’ will cause the FIFO to re-align to the LVDS receiver. If LVDS bank 0 is in use, it will be used for alignment. Otherwise, LVDS bank 2 will be used. (Continuous alignment is not performed because the LVDS clock is asynchronous to the DAC clock and may cause realignment each time alignment is performed.) The alignment will cause a CLK_REALIGNED_ALM if realignment occurs. This bit should only be set while DP_EN=1, the DAC data path is zeroed (TXENABLE ball or register is low), and NCO_EN=0.

Note: This bit aligns to the current internal operating alignment of the LVDS receiver circuitry. Alignment does not wait for an actual strobe to be provided on the LVDS bank and can be performed even if a strobe is not currently being provided. However, it is important that an LVDS strobe be provided to align the LVDS receiver prior to aligning the FIFO with this bit.

Note: Once the system has been synchronized to SYSREF, this bit cannot be used again until the part has been reset or DP_EN has been returned to zero.
0SYSREF_ALIGN_ENR/W0hWhen this register is set, the FIFO re-aligns to each detected SYSREF edge. This bit should only be high while DP_EN=1, transmit_en_a=0, transmit_en_b=0, and NCO_EN=0. When a mis-aligned SYSREF edge occurs while this bit is set, CLK_REALIGNED_ALM will be set and the clocks will re-align. When this register is clear, the FIFO does not re-align on SYSREF edges. However, mis-aligned SYSREF edges are still reported in CLK_ALIGNMENT_ALM.

Note: It is possible that a SYSREF edge provided very near the SPI clock edge that commits the write of this bit will be processed for alignment even though it technically arrived at the chip pins prior to the SPI clock edge.

7.5.2.34 NCO_SYNC Register (Address = 300h) [reset = 00h]

NCO_SYNC is shown in Figure 7-58 and described in Table 7-44.

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NCO Sync Source Select (default: 0x00)

Note: This register should only be changed when NCO_EN=0.

Note: You cannot use the same SYSREF edge to align the FIFO and to sync the NCO since FIFO alignment requires NCO_EN=0.

Figure 7-58 NCO_SYNC Register
76543210
RESERVEDNCO_CHG_SRC_BNCO_CHG_SRC_ARESERVEDNCO_SYNC_SRC
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-44 NCO_SYNC Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0h
5NCO_CHG_SRC_BR/W0h0: NCO B will use the NCO accumulator specified in NCO_SEL_B.
1: NCO B accumulator selection is performed using the nco_sel[3:0] and nco_banksel inputs and occurs on the rising edge of trig_c.

Note: If nco_sel[3:0] and nco_banksel are not changed synchronous to trig_c, the part may temporarily switch to an unintended accumulator before switching to the correct one.
4NCO_CHG_SRC_AR/W0h0: NCO A will use the NCO accumulator specified in NCO_SEL_A.
1: NCO A selection is performed using the nco_sel[3:0] and nco_banksel inputs and occurs on the rising edge of trig_c.

Note: If nco_sel[3:0] and nco_banksel are not changed synchronous to trig_c, the part may temporarily switch to an unintended NCO before switching to the correct one.
3-2RESERVEDR/W0h
1-0NCO_SYNC_SRCR/W0h0: Setting SPI_SYNC will immediately reset the NCO accumulators (both A & B)
1: Setting SPI_SYNC will cause the NCO accumulators to reset on the next SYSREF rising edge.
2: Setting SPI_SYNC will cause the NCO accumulators to reset on the next rising edge of trig_c with nco_banksel = 1.
3: RESERVED

7.5.2.35 NCO_SPISEL Register (Address = 301h) [reset = 0000h]

NCO_SPISEL is shown in Figure 7-59 and described in Table 7-45.

Note: This register should only be changed when NCO_EN=0 or NCO_CHG_BLK=1.

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NCO Fast-Frequency Hopping Frequency Selection (default: 0x0000)

Figure 7-59 NCO_SPISEL Register
15141312111098
RESERVEDNCO_SEL_B
R/W-0hR/W-0h
76543210
RESERVEDNCO_SEL_A
R/W-0hR/W-0h
Table 7-45 NCO_SPISEL Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR/W0h
12-8NCO_SEL_BR/W0hSelects which frequency/phase values to use for NCO B if NCO_CHG_SRC_B = 0. The MSB here selects which NCO bank to use. (0=A, 1=B)
7-5RESERVEDR/W0h
4-0NCO_SEL_AR/W0hSelects which frequency/phase values to use for NCO A if NCO_CHG_SRC_A = 0. The MSB here selects which NCO bank to use. (0=A, 1=B)

7.5.2.36 NCO_BANKCFG Register (Address = 303h) [reset = 00h]

NCO_BANKCFG is shown in Figure 7-60 and described in Table 7-46.

Note: This register should only be changed when NCO_EN=0 or NCO_CHG_BLK=1.

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NCO Bank Configuration (default: 0x00)

Figure 7-60 NCO_BANKCFG Register
76543210
RESERVEDNCO_BANKCFG
R/W-0hR/W-0h
Table 7-46 NCO_BANKCFG Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0h
1-0NCO_BANKCFGR/W0h0: The value of nco_sel[3:0] sampled on trig_c selects the respective A and B channel NCO accumulator.
1: The value of nco_sel[3:0] sampled on trig_c selects the same NCO accumulator for both A and B channels based on the value of nco_banksel (0=A, 1=B). This makes it look like there are 32 NCO accumulators and nco_banksel is the MSB of nco_sel.
2: The value of nco_sel[3:0] sampled on trig_c changes only the accumulator for the NCO selected by nco_banksel. (0=A, 1=B). Only one of the two NCO’s can change per trig_c in this mode. In this case, nco_banksel is more like an NCO select.
3: RESERVED

NOTE: This register should only be changed when NCO_EN=0.

7.5.2.37 NCO_EN Register (Address = 308h) [reset = 00h]

NCO_EN is shown in Figure 7-61 and described in Table 7-47.

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NCO Enable (default: 0x00)

Figure 7-61 NCO_EN Register
76543210
RESERVEDNCO_EN
R/W-0hR/W-0h
Table 7-47 NCO_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0NCO_ENR/W0hSetting this bit enables NCO operation. When this bit is cleared, the entire NCO is held in reset. This bit should be set after the NCO operation is configured and DP_EN=1.

7.5.2.38 SPI_SYNC Register (Address = 310h) [reset = 00h]

SPI_SYNC is shown in Figure 7-62 and described in Table 7-48.

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SPI Sync (default: 0x00)

Figure 7-62 SPI_SYNC Register
76543210
RESERVEDSPI_SYNC
R/W-0hR/W-0h
Table 7-48 SPI_SYNC Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0SPI_SYNCR/W0hWriting ‘1’ to this register when it is ‘0’ will trigger synchronization events that are bound to this register (see NCO_SYNC_SRC). This register will return the last value written.

7.5.2.39 NCO_CHG_BLK Register (Address = 320h) [reset = 00h]

NCO_CHG_BLK is shown in Figure 7-63 and described in Table 7-49.

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NCO Change Blocking (default: 0x00)

Figure 7-63 NCO_CHG_BLK Register
76543210
RESERVEDNCO_CHG_BLK
R/W-0hR/W-0h
Table 7-49 NCO_CHG_BLK Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0NCO_CHG_BLKR/W0hWhen set, changes to NCO_SEL_A, NCO_SEL_B, FFH_FREQ_A, FFH_FREQ_B, FFH_PHASE_A, and FFH_PHASE_B, are not propagated to the high speed clocks and the NCOs continue to use their current values. When cleared, the NCO’s use the values from these registers. The user must set this if changing any of these values while NCO_EN=1.

Note: Phase continuous operation is only supported from FFH_FREQ_A[0] and FFH_FREQ_B[0].

Note: Changing frequency values during operation only makes sense if phase coherency is unimportant since the user cannot control when the frequency change will take effect.

7.5.2.40 NCO_RAMPRATE Register (Address = 330h) [reset = 00h]

NCO_RAMPRATE is shown in Figure 7-64 and described in Table 7-50.

Note: If NCO_MODE=1 and both DACs use the NCO source and transmit_en_a != transmit_en_b, the rampup/rampdown behavior is undefined.

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NCO Ramp Rate Control (default: 0x00)

Figure 7-64 NCO_RAMPRATE Register
76543210
RESERVEDNCO_RAMPRATE
R/W-0hR/W-0h
Table 7-50 NCO_RAMPRATE Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0h
2-0NCO_RAMPRATER/W0hEach of the NCO sources is linearly ramped up/down over the specified number of DEVCLK cycles when transmission is enabled/disabled.
0: 0 DEVCLK cycles
1: 16 DEVCLK cycles
2: 32 DEVCLK cycles
3: 64 DEVCLK cycles
4: 128 DEVCLK cycles
5: 256 DEVCLK cycles
6: 512 DEVCLK cycles
7: 1024 DEVCLK cycles

Note: This register should only be changed when TXENABLE (ball or register) is low.

7.5.2.41 NCO_CONFIG Register (Address = 331h) [reset = 02h]

NCO_CONFIG is shown in Figure 7-65 and described in Table 7-51.

Note: This register should only be changed when TXENABLE (ball or register) is low.

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NCO Configuration (default: 0x02)

Figure 7-65 NCO_CONFIG Register
76543210
RESERVEDNCO_DITH_ENNCO_MODE
R/W-0hR/W-1hR/W-0h
Table 7-51 NCO_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR/W0h
1NCO_DITH_ENR/W1hSetting this bit causes the NCO to use sub-LSB dither prior to rounding to smooth out the quantization noise. It may be useful to turn this off for certain frequencies where the quantization error is not a concern.
0NCO_MODER/W0h0: NCOs operate independently
1: NCOs are summed to create the final NCO output. If both DACA and DACB use the NCO source, they will both get the summed value in this mode.


7.5.2.42 NCO_GAIN_A Register (Address = 332h) [reset = 0003h]

NCO_GAIN_A is shown in Figure 7-66 and described in Table 7-52.

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Gain backoff for NCO A (default: 0x0003)

Figure 7-66 NCO_GAIN_A Register
15141312111098
NCO_GAIN_A
R/W-3h
76543210
NCO_GAIN_A
R/W-3h
Table 7-52 NCO_GAIN_A Register Field Descriptions
BitFieldTypeResetDescription
15-0NCO_GAIN_AR/W3hThis setting is the gain backoff for NCO A. This backoff is applied independent of NCO_MODE. The gain is equal to 1-(x/216).

Note: Setting DITH_EN_A>0 automatically reduces the gain to prevent clipping from the NCO. The value programmed here is added to the required backoff for dither. The final gain will saturate at zero.

Note: Setting this value below the default will result in saturation for some frequencies.

Note: This register should only be changed when NCO_EN=0.

7.5.2.43 NCO_GAIN_B Register (Address = 334h) [reset = 0003h]

NCO_GAIN_B is shown in Figure 7-67 and described in Table 7-53.

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Gain backoff for NCO B (default: 0x0003)

Figure 7-67 NCO_GAIN_B Register
15141312111098
NCO_GAIN_B
R/W-3h
76543210
NCO_GAIN_B
R/W-3h
Table 7-53 NCO_GAIN_B Register Field Descriptions
BitFieldTypeResetDescription
15-0NCO_GAIN_BR/W3hThis setting is the gain backoff for NCO B. This backoff is applied independent of NCO_MODE. The gain is equal to 1-(x/216).

Note: Setting DITH_EN_B>0 automatically reduces the gain to prevent clipping from the NCO. The value programmed here is added to the required backoff for dither. The final gain will saturate at zero.

Note: Setting this value below the default will result in saturation for some frequencies.

Note: This register should only be changed when NCO_EN=0.

7.5.2.44 FFH_FREQ_A[15:0] Register (Address = 400h) [reset = 0h]

FFH_FREQ_A[15:0] is shown in Figure 7-68 and described in Table 7-54.

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Frequency Word for Fast-Frequency Hopping (default: {16{0x00000000}}). The FFH setting for NCO_SEL_A=0 will be at the lowest address, and then increment by 4*n for NCO_SEL_A = n.

Figure 7-68 FFH_FREQ_A[15:0] Register
313029282726252423222120191817161514131211109876543210
FFH_FREQ_A
R/W-0h
Table 7-54 FFH_FREQ_A[15:0] Register Field Descriptions
BitFieldTypeResetDescription
31-0FFH_FREQ_AR/W0hThe NCO frequency (FNCO) is:
FNCO = FREQ_A * 2-32 * FDAC
FDAC is the sample frequency of the DAC. FREQ_A is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:
FREQ_A = 232 * FNCO /FDAC

Note: Changing this register after the NCO has been synchronized will result in non-deterministic NCO phase. If deterministic phase is required, the NCO should be re-synchronized after changing this register.

Note: This register should only be changed when NCO_EN=0 or NCO_CHG_BLK=1.

7.5.2.45 FFH_FREQ_B[15:0] Register (Address = 440h) [reset = 0h]

FFH_FREQ_B[15:0] is shown in Figure 7-69 and described in Table 7-55.

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Frequency Word for Fast-Frequency Hopping (default: {16{0x00000000}}). The FFH setting for NCO_SEL_B=0 will be at the lowest address, and then increment by 4*n for NCO_SEL_B = n.

Figure 7-69 FFH_FREQ_B[15:0] Register
313029282726252423222120191817161514131211109876543210
FFH_FREQ_B
R/W-0h
Table 7-55 FFH_FREQ_B[15:0] Register Field Descriptions
BitFieldTypeResetDescription
31-0FFH_FREQ_BR/W0hThe NCO frequency (FNCO) is:
FNCO = FREQ_B * 2-32 * FDAC
FDAC is the sample frequency of the DAC. FREQ_B is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:
FREQ_B = 232 * FNCO /FDAC

Note: Changing this register after the NCO has been synchronized will result in non-deterministic NCO phase. If deterministic phase is required, the NCO should be re-synchronized after changing this register.

Note: This register should only be changed when NCO_EN=0 or NCO_CHG_BLK=1.

7.5.2.46 FFH_PHASE_A[15:0] Register (Address = 480h) [reset = 0h]

FFH_PHASE_A[15:0] is shown in Figure 7-70 and described in Table 7-56.

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Phase Word for Fast-Frequency Hopping (default: {16{0x0000}}). The FFH setting for NCO_SEL_A=0 will be at the lowest address, and then increment by 2*n for NCO_SEL_A = n.

Figure 7-70 FFH_PHASE_A[15:0] Register
15141312111098
FFH_PHASE_A
R/W-0h
76543210
FFH_PHASE_A
R/W-0h
Table 7-56 FFH_PHASE_A[15:0] Register Field Descriptions
BitFieldTypeResetDescription
15-0FFH_PHASE_AR/W0hPhase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE_A * 2-16 * 2π. This register can be interpreted as signed or unsigned.

Note: This register should only be changed when NCO_EN=0 or NCO_CHG_BLK=1.

7.5.2.47 FFH_PHASE_B[15:0] Register (Address = 4A0h) [reset = 0h]

FFH_PHASE_B[15:0] is shown in Figure 7-71 and described in Table 7-57.

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Phase Word for Fast-Frequency Hopping (default: {16{0x0000}}). The FFH setting for NCO_SEL_B=0 will be at the lowest address, and then increment by 2*n for NCO_SEL_B = n.

Figure 7-71 FFH_PHASE_B[15:0] Register
15141312111098
FFH_PHASE_B
R/W-0h
76543210
FFH_PHASE_B
R/W-0h
Table 7-57 FFH_PHASE_B[15:0] Register Field Descriptions
BitFieldTypeResetDescription
15-0FFH_PHASE_BR/W0hPhase is added late so this register can be written during operation to change the phase without needing to reset the NCO.

This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE_B * 2-16 * 2π. This register can be interpreted as signed or unsigned.

Note: This register should only be changed when NCO_EN=0 or NCO_CHG_BLK=1.

7.5.2.48 TS_TEMP Register (Address = 700h) [reset = 0h]

TS_TEMP is shown in Figure 7-72 and described in Table 7-58.

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Temperature Reading in Celsius (read-only)

Figure 7-72 TS_TEMP Register
76543210
TS_TEMP
R-0h
Table 7-58 TS_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-0TS_TEMPR0h

Returns the temperature sensor reading in degrees Celsius. This is a signed value.

Note: Reads of this register require slower SPI timing. See AC-Spec -> SPI Interface.

Note: The temperature sensor cannot perform a reading unless SLEEP=0, MODE=0 and TS_SLEEP=0.

7.5.2.49 TS_SLEEP Register (Address = 701h) [reset = 00h]

TS_SLEEP is shown in Figure 7-73 and described in Table 7-59.

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Temperature Sensor Sleep (default: 0x00)

Figure 7-73 TS_SLEEP Register
76543210
RESERVEDTS_SLEEP
R/W-0hR/W-0h
Table 7-59 TS_SLEEP Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0TS_SLEEPR/W0hIf temperature conversions are not needed, set this bit to sleep the temperature sensor.

7.5.2.50 IOTEST_CFG Register (Address = 710h) [reset = 00h]

IOTEST_CFG is shown in Figure 7-74 and described in Table 7-60.

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IOTEST Configuration (default: 0x00)

Figure 7-74 IOTEST_CFG Register
76543210
IOTEST_EN[3:0]RESERVEDIOTEST_STRB_LOCKIOTEST_CONT
R/W-0hR/W-0hR/W-0hR/W-0h
Table 7-60 IOTEST_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-4IOTEST_EN[3:0]R/W0h

When set, IOTEST_EN[ i] enables IO testing for LVDS bank i (assuming that the LVDS bank is currently configured for operation).

Note: When any bit of this register is set, no LVDS data is passed through to the output of the DAC.

3-2RESERVEDR/W0h
1IOTEST_STRB_LOCKR/W0hSetting this bit prevents the LVDS strobe from re-aligning the LVDS counters. (It does not prevent the strobe alignment alarms.) Use this to allow a pattern on the strobe pin that is different from the normal strobe pattern.
0IOTEST_CONTR/W0h

0: IOTEST will stop when the first error is detected

1: IOTEST will run until manually stopped

7.5.2.51 IOTEST_CTRL Register (Address = 711h) [reset = 00h]

IOTEST_CTRL is shown in Figure 7-75 and described in Table 7-61.

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IOTEST Control (default: 0x00)

Figure 7-75 IOTEST_CTRL Register
76543210
RESERVEDIOTEST_TRIG
R/W-0hR/W-0h
Table 7-61 IOTEST_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR/W0h
0IOTEST_TRIGR/W0hWriting ‘1’ to this register when it is ‘0’ will start the IOTEST at the beginning of the next frame and clear the IOTEST_STAT* registers. Writing ‘0’ to this register will stop the IOTEST if it is running. If this register is ‘1’, use IOTEST_RUN to see if the test is actually running or has been stopped due to a captured failure.

7.5.2.52 IOTEST_SUM Register (Address = 712h) [reset = 0h]

IOTEST_SUM is shown in Figure 7-76 and described in Table 7-62.

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IOTEST Status (read-only)

Figure 7-76 IOTEST_SUM Register
76543210
IOTEST_RUN[3:0]IOTEST_MISS3_SUMIOTEST_MISS2_SUMIOTEST_MISS1_SUMIOTEST_MISS0_SUM
R-0hR-0hR-0hR-0hR-0h
Table 7-62 IOTEST_SUM Register Field Descriptions
BitFieldTypeResetDescription
7-4IOTEST_RUN[3:0]R0hIOTEST_RUN[i] will be set any time the IOTEST is running on LVDS bank i.
3IOTEST_MISS3_SUMR0hThis bit will be set any time a failure is reported in IOTEST_MISS3. This bit is cleared by clearing the failures in IOTEST_MISS3.
2IOTEST_MISS2_SUMR0hThis bit will be set any time a failure is reported in IOTEST_MISS2. This bit is cleared by clearing the failures in IOTEST_MISS2.
1IOTEST_MISS1_SUMR0hThis bit will be set any time a failure is reported in IOTEST_MISS1. This bit is cleared by clearing the failures in IOTEST_MISS1.
0IOTEST_MISS0_SUMR0hThis bit will be set any time a failure is reported in IOTEST_MISS0. This bit is cleared by clearing the failures in IOTEST_MISS0.

7.5.2.53 IOTEST_PAT[7:0] Register (Address = 720h) [reset = 0h]

IOTEST_PAT[7:0] is shown in Figure 7-77 and described in Table 7-63.

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IOTEST Pattern Memory (default: {8{0x0000}}).

This is the 8-word pattern memory containing the 16-bit words for the LVDS IOTEST. The first sample of the frame should be at the lowest address.

Each of the 8 words has this format:

Figure 7-77 IOTEST_PAT[7:0] Register
15 14 13 12 11 10 9 8
RESERVED IOTEST_DATA[12:8]
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
IOTEST_DATA[7:0]
R/W-0h
Table 7-63 IOTEST_PAT[7:0] Register Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R/W 0h
12-0 IOTEST_DATA R/W 0h

[12]: Defines the expected state of the strobe pin.

[11:0]: Defines the expected state of the data pins.

Note: The falling edge data for the strobe pin should always be set to zero.

7.5.2.54 IOTEST_STAT0 Register (Address = 750h) [W1C, reset = NA]

IOTEST_STAT0 is shown in Figure 7-78 and described in Table 7-64.

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IOTEST Bank0 Failure Status

Figure 7-78 IOTEST_STAT0 Register
15141312111098
RESERVED IOTEST_MISS0[12:8]
R/W-0h W1C
76543210
IOTEST_MISS0[7:0]
W1C
Table 7-64 IOTEST_STAT0 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR/W0h
12-0IOTEST_MISS0W1CNA

[12]: Failure on strobe pin

[11:0]: Failure on indicated data pin

7.5.2.55 IOTEST_STAT1 Register (Address = 752h) [W1C, reset = NA]

IOTEST_STAT1 is shown in Figure 7-79 and described in Table 7-65.

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IOTEST Bank1 Failure Status

Figure 7-79 IOTEST_STAT1 Register
15141312111098
RESERVED IOTEST_MISS1[12:8]
R/W-0h W1C
76543210
IOTEST_MISS1[7:0]
W1C
Table 7-65 IOTEST_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR/W0h
12-0IOTEST_MISS1W1CNA

[12]: Failure on strobe pin

[11:0]: Failure on indicated data pin

7.5.2.56 IOTEST_STAT2 Register (Address = 754h) [W1C, reset = NA]

IOTEST_STAT2 is shown in Figure 7-80 and described in Table 7-66.

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IOTEST Bank2 Failure Status (write-to-clear)

Figure 7-80 IOTEST_STAT2 Register
15141312111098
RESERVED IOTEST_MISS2[12:8]
R/W-0h W1C
76543210
IOTEST_MISS2[7:0]
W1C
Table 7-66 IOTEST_STAT2 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR/W0h
12-0IOTEST_MISS2W1CNA

[12]: Failure on strobe pin

[11:0]: Failure on indicated data pin

7.5.2.57 IOTEST_STAT3 Register (Address = 756h) [reset = 0h]

IOTEST_STAT3 is shown in Figure 7-81 and described in Table 7-67.

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IOTEST Bank3 Failure Status (write-to-clear)

Figure 7-81 IOTEST_STAT3 Register
15141312111098
RESERVED IOTEST_MISS3[12:8]
R/W-0h W1C
76543210
IOTEST_MISS3[7:0]
W1C
Table 7-67 IOTEST_STAT3 Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR/W0h
12-0IOTEST_MISS3W1CNA

[12]: Failure on strobe pin

[11:0]: Failure on indicated data pin

7.5.2.58 IOTEST_CAP0[7:0] Register (Address = 760h) [read only, reset = NA]

IOTEST_CAP0[7:0] is shown in Figure 7-82 and described in Table 7-68.

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IOTEST Bank0 Capture Memory (read-only)

This is the 8-word capture memory containing the 13-bit captured words from the bank. If the test was run with IOTEST_CONT = 0 and IOTEST_MISS0 != 0, this memory will contain the captured frame with the error. Since it contains the entire frame, more than one error may be present. The first sample of the frame will be at the lowest address.

Note: The capture memory should only be read while IOTEST_RUN[0] = 0.

Figure 7-82 IOTEST_CAP0[7:0] Register
15141312111098
RESERVED IOTEST_CAP_DATA[12:8]
R-0h R-0h
76543210
IOTEST_CAP_DATA[7:0]
R-0h
Table 7-68 IOTEST_CAP0[7:0] Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h
12-0IOTEST_CAP_DATAR0h

[12]: Captured data for strobe pin

[11:0]: Captured data for indicated data pin

7.5.2.59 IOTEST_CAP1[7:0] Register (Address = 770h) [reset = 0h]

IOTEST_CAP1[7:0] is shown in Figure 7-83 and described in Table 7-69.

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IOTEST Bank1 Capture Memory (read-only)

This is the 8-word capture memory containing the 13-bit captured words from the bank. If the test was run with IOTEST_CONT = 0 and IOTEST_MISS0 != 0, this memory will contain the captured frame with the error. Since it contains the entire frame, more than one error may be present. The first sample of the frame will be at the lowest address.

Note: The capture memory should only be read while IOTEST_RUN[1] = 0.

Figure 7-83 IOTEST_CAP1[7:0] Register
15141312111098
RESERVED IOTEST_CAP_DATA[12:8]
R-0h R-0h
76543210
IOTEST_CAP_DATA[7:0]
R-0h
Table 7-69 IOTEST_CAP1[7:0] Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h
12-0IOTEST_CAP_DATAR0h

[12]: Captured data for strobe pin

[11:0]: Captured data for indicated data pin

7.5.2.60 IOTEST_CAP2[7:0] Register (Address = 780h) [reset = 0h]

IOTEST_CAP2[7:0] is shown in Figure 7-84 and described in Table 7-70.

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IOTEST Bank2 Capture Memory (read-only)

This is the 8-word capture memory containing the 13-bit captured words from the bank. If the test was run with IOTEST_CONT = 0 and IOTEST_MISS2 != 0, this memory will contain the captured frame with the error. Since it contains the entire frame, more than one error may be present. The first sample of the frame will be at the lowest address.

Note: The capture memory should only be read while IOTEST_RUN[2] = 0.

Figure 7-84 IOTEST_CAP2[7:0] Register
15141312111098
RESERVED IOTEST_CAP_DATA[12:8]
R-0h R-0h
76543210
IOTEST_CAP_DATA[7:0]
R-0h
Table 7-70 IOTEST_CAP2[7:0] Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h
12-0IOTEST_CAP_DATAR0h

[12]: Captured data for strobe pin

[11:0]: Captured data for indicated data pin

7.5.2.61 IOTEST_CAP3[7:0] Register (Address = 790h) [reset = 0h]

IOTEST_CAP3[7:0] is shown in Figure 7-85 and described in Table 7-71.

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IOTEST Bank3 Capture Memory (read-only)

This is the 8-word capture memory containing the 13-bit captured words from the bank. If the test was run with IOTEST_CONT = 0 and IOTEST_MISS3 != 0, this memory will contain the captured frame with the error. Since it contains the entire frame, more than one error may be present. The first sample of the frame will be at the lowest address.

Note: The capture memory should only be read while IOTEST_RUN[3] = 0.

Figure 7-85 IOTEST_CAP3[7:0] Register
15141312111098
RESERVED::
R-0hR-0hR-0h
76543210
IOTEST_CAP_DATA[7:0]
R-0h
Table 7-71 IOTEST_CAP3[7:0] Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR0h
12-0IOTEST_CAP_DATAR0h

[12]: Captured data for strobe pin

[11:0]: Captured data for indicated data pin

7.5.2.62 SYNC_STATUS Register (Address = 800h) [W1C, reset = NA]

SYNC_STATUS is shown in Figure 7-86 and described in Table 7-72.

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Synchronization Status (default: 0x00)

Figure 7-86 SYNC_STATUS Register
76543210
LVDS_STROBE_DET[3:0]RESERVEDSYSREF_DET
W1CR/W-0hW1C
Table 7-72 SYNC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7-4LVDS_STROBE_DET[3:0]W1CNA[i]: Bit is set when a strobe is detected for LVDS bank i. Write 1 to clear the bit and allow it to be re-detected. These bits are also cleared on the rising edge of LVDS_STROBE_ALIGN.
3-1RESERVEDR/W0h
0SYSREF_DETW1CNAThis bit is set when a SYSREF is detected. Write 1 to clear the bit and allow it to be re-detected. This bit is also cleared on the rising edge of SYSREF_ALIGN_EN.

7.5.2.63 FIFO_ALM Register (Address = 820h) [W1C, reset = NA]

FIFO_ALM is shown in Figure 7-87 and described in Table 7-73.

Note: These registers will only detect alarms on input data transitions. Constant input data will not produce alarms.

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FIFO Alarm Status (default: 0x00)

Figure 7-87 FIFO_ALM Register
76543210
FIFO_EMPTY_ALMFIFO_FULL_ALM
W1CW1C
Table 7-73 FIFO_ALM Register Field Descriptions
BitFieldTypeResetDescription
7-4FIFO_EMPTY_ALMW1C0hFIFO_EMPTY_ALM[i] is set if the FIFO for bank i is almost empty. FIFOs that are not enabled will never generate an alarm. Write 1 to a bit to clear the alarm.
3-0FIFO_FULL_ALMW1C0hFIFO_FULL_ALM[i] is set if the FIFO for bank i is almost full. FIFOs that are not enabled will never generate an alarm. Write 1 to a bit to clear the alarm.

7.5.2.64 LVDS_ALM Register (Address = 821h) [W1C, reset = NA]

LVDS_ALM is shown in Figure 7-88 and described in Table 7-74.

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LVDS Strobe Alarm (default: 0x00)

Figure 7-88 LVDS_ALM Register
76543210
LVDS_CLK_ALMSTROBE_ALM
W1CW1C
Table 7-74 LVDS_ALM Register Field Descriptions
BitFieldTypeResetDescription
7-4LVDS_CLK_ALMW1C0hLVDS_CLK_ALM[i] is set if the respective LVDS bank is configured for use and the LVDS clock is not running. The LVDS clock must miss at least half of its edges within 8 LVDS periods to ensure detection. Write 1 to a bit to clear the alarm.
3-0STROBE_ALMW1C0hSTROBE_ALM[i] is set if the strobe for LVDS bank i arrives at an unexpected position. Unless IOTEST_STRB_LOCK was set when the error occured, this has caused the input side of the FIFO to re-align. Write 1 to a bit to clear the alarm.

7.5.2.65 SYS_ALM Register (Address = 822h) [W1C, reset = NA]

SYS_ALM is shown in Figure 7-89 and described in Table 7-75.

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System Alarm Status (default: 0x00)

Figure 7-89 SYS_ALM Register
76543210
RESERVEDTRIG_REALIGNED_ALMCLK_ALIGNMENT_ALMCLK_REALIGNED_ALM
R/W-0hW1CW1CW1C
Table 7-75 SYS_ALM Register Field Descriptions
BitFieldTypeResetDescription
7-3RESERVEDR/W0h
2TRIG_REALIGNED_ALMW1CNAThis bit is set if SYSREF re-aligns the trigger clock divider. This generally occurs if the SYSREF period is not correct. The SYSREF period must be an integer multiple of the Trigger Clock period. This is not intended to detect small changes in SYSREF alignment. The CLK_ALIGNMENT_ALM should be used for this purpose. Write 1 to clear the alarm.
1CLK_ALIGNMENT_ALMW1CNAThis bit is set if SYSREF_ALIGN_EN=0, and a SYSREF edge is detected at an incorrect alignment. Write 1 to clear the alarm.
0CLK_REALIGNED_ALMW1CNAThis bit is set if a detected SYSREF edge or LVDS strobe re-aligns the clocks. Write 1 to clear the alarm.

7.5.2.66 ALM_MASK Register (Address = 823h) [reset = 00h]

ALM_MASK is shown in Figure 7-90 and described in Table 7-76.

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Alarm Mask (default: 0x00)

Figure 7-90 ALM_MASK Register
76543210
FIFO_ALM_MASKLVDS_CLK_ALM_MASKSTROBE_ALM_MASKRESERVEDTRIG_REALIGNED_ALM_MASKCLK_ALIGNMENT_ALM_MASK CLK_REALIGNED_ALM_MASK
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0b R/W-0b
Table 7-76 ALM_MASK Register Field Descriptions
BitFieldTypeResetDescription
7FIFO_ALM_MASKR/W0hWhen set, alarms from the FIFO_ALM registers are masked and will not impact the alarm output.
6LVDS_CLK_ALM_MASKR/W0hWhen set, alarms from the LVDS_CLK_ALM registers are masked and will not impact the alarm output.
5STROBE_ALM_MASKR/W0hWhen set, alarms from the STROBE_ALM registers are masked and will not impact the alarm output.
4-3RESERVEDR/W0h
2TRIG_REALIGNED_ALM_MASKR/W0bWhen set, alarms from the TRIG_REALIGNED_ALM register are masked and will not impact the alarm output.
1CLK_ALIGNMENT_ALM_MASK R/W0b When set, alarms from the CLK_ALIGNMENT_ALM register are masked and will not impact the alarm output.
0 CLK_REALIGNED_ALM_MASK R/W 0b When set, alarms from the CLK_REALIGNED_ALM register are masked and will not impact the alarm output.

7.5.2.67 MUTE_MASK Register (Address = 824h) [reset = 07h]

MUTE_MASK is shown in Figure 7-91 and described in Table 7-77.

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DAC Mute Mask (default: 0x07)

Figure 7-91 MUTE_MASK Register
76543210
FIFO_MUTE_MASKLVDS_CLK_MUTE_MASKSTROBE_MUTE_MASKRESERVEDTRIG_REALIGNED_MUTE_MASKCLK_ALIGNMENT_MUTE_MASK CLK_REALIGNED_MUTE_MASK
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1bR/W-1b R/W-1b
Table 7-77 MUTE_MASK Register Field Descriptions
BitFieldTypeResetDescription
7FIFO_MUTE_MASKR/W0hAlarms from the FIFO_ALM registers will mute the DAC unless this bit is set.
6LVDS_CLK_MUTE_MASKR/W0hAlarms from the LVDS_CLK_ALM registers will mute the DAC unless this bit is set.
5STROBE_MUTE_MASKR/W0hAlarms from the STROBE_ALM registers will mute the DAC unless this bit is set.
4-3RESERVEDR/W0h
2TRIG_REALIGNED_MUTE_MASKR/W1bAlarms from the TRIG_REALIGNED_ALM register will mute the DAC unless this bit is set.
1CLK_ALIGNMENT_MUTE_MASKR/W1bAlarms from the CLK_ALIGNMENT_ALM register will mute the DAC unless this bit is set.
0 CLK_REALIGNED_MUTE_MASK 1b Alarms from the CLK_REALIGNED_ALM register will mute the DAC unless this bit is set.

7.5.2.68 FUSE_STATUS Register (Address = 900h) [reset = 00h]

FUSE_STATUS is shown in Figure 7-92 and described in Table 7-78.

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Fuse Status (default: variable)

Figure 7-92 FUSE_STATUS Register
7 6 5 4 3 2 1 0
RESERVED FUSE_DONE
R-00h R-0b
Table 7-78 FUSE_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-1 RESERVED R 01h RESERVED
FUSE_DONE Fuse Done R 0b Returns '1' when the fuse controller has finished loading registers from the FuseROM.

7.5.2.69 SYSREF_PS_EN Register (Address = B02h) [reset = 0x00]

SYSREF_PS_EN is shown in Figure 7-93 and described in Table 7-79. This function is only available for CHIP_VERSION=2.

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SYSREF_PS_EN (default: 0x00)

Figure 7-93 SYSREF_PS_EN Register
7 6 5 4 3 2 1 0
RESERVED RESERVED - always write 0x0 SYSREF_PS_EN
R/W-0h R/W-0h R/W-0b
Table 7-79 SYSREF_PS_EN Register Field Descriptions
Bit Field Type Reset Description
7-5 RESERVED R/W 000b RESERVED
4-1 RESERVED R/W 0x0 RESERVED - always write 0x0
0 SYSREF_PS_EN R/W 0 When set, SYSREF_POS will contain 1’s for all positions that have been detected as near the SYSREF edge since this bit was set. When cleared, SYSREF_POS will only contain 1’s for the last SYSREF edge that was detected.