The DRV870xD-Q1 device is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is disabled, the half-bridge FETs are disabled to the Hi-Z state, and the AVDD and DVDD regulators are disabled.
The t(SLEEP) time must elapse after a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV870xD-Q1 device is brought out of sleep mode automatically if the nSLEEP pin is brought high.
The t(WAKE) time must elapse before the outputs change state after wakeup.
On the DRV8703D-Q1 device, the SPI settings are reset when coming out of UVLO or exiting sleep mode.
While the nSLEEP pin is brought low, both external half-bridge FETs are disabled. The high-side gate pin, GH, are pulled to the output node, SH, by an internal resistor and the low-side gate pin, GL, are pulled to ground.
When the VM voltage is not applied and during the power-on time (ton) the outputs are disabled using weak pulldown resistors between the GH and SH pins and the GL and GND pins.
The MODE pin controls the device-logic operation for the PWM input mode. This operation is latched on power up or when exiting sleep mode.