Overcurrent is sensed by monitoring the VDS voltage drop across the external FETs. If the voltage across a driven FET exceeds the VDS(OCP) level for longer than the OCP deglitch time, an OCP event is recognized. Both FETs in the half-bridge are disabled, and the nFAULT pin is driven low. The OCP bit of the DRV8703D-Q1 device is set. The drive re-enables after the t(RETRY) time has passed. The nFAULT pin becomes high again after the retry time.
If the fault condition is still present, the cycle repeats. If the fault is no longer present, normal operation resumes and the nFAULT pin goes high. The OCP bit on the DRV8703D-Q1 remains set until cleared by writing to the CLR_FLT bit. In addition to this FET VDS monitor, an overcurrent condition is detected if the voltage at the SP pin exceeds VSP(OCP) and the nFAULT pin is driven low. The OCP bit in the DRV8703-Q1 device is set.