The GH and GL pins are monitored such that if the voltage on the external FET gate does not increase or decrease after the t(DRIVE) time, a gate driver fault is detected. This fault occurs if the GH or GL pins are shorted to the GND, SH, or VM pin. Additionally, a gate-driver fault occurs if the selected IDRIVE setting is not sufficient to turn on the external FET. Both FETs in the half-bridge are disabled, and the nFAULT pin is driven low. The GDF bit of the DRV8703D-Q1 device is set. The driver re-enables after the OCP retry period (t(RETRY)) has passed. The nFAULT pin is released after the operation has resumed but the GDF bit on the DRV8703D-Q1 device remains set until cleared by writing to the CLR_FLT bit.