Figure 7-5 shows APLL2 in cascaded mode from APLL1. VCO1 is held near the nominal center frequency of 2457.6MHz while APLL2 acquires lock. Subsequently, APLL1 locks the VCO1 frequency to the external XO input and operates in free-run mode. Cascaded PLLs lock to a divided frequency from the source VCO. Once a valid DPLL reference input is detected beyond a minimum valid time, the DPLLs begin lock acquisition. Each DPLL TDC compares the phase of the selected reference input clock and the FB divider clock from the respective VCO and generates a digital correction word corresponding to the phase error. At beginning, the TDC simply cancels out the phase error with no filtering correction word. Then subsequent correction words are filtered by the DLF, and the DLF output adjusts the APLL N divider numerator to pull the VCO frequency into lock with the reference input.

Using the VCBO as a cascade source to APLL2 provides the APLL a high-frequency, ultra-low-jitter reference clock. This unique cascading feature can provide improved close in phase noise performance if the XO/TCXO/OCXO is a low frequency or has poor phase noise performance. Note that in cascaded DPLL operation the best jitter performance and frequency stability is achieved after DPLL1 locked.

DPLL1 lock status impacts the DPLL2 lock status. If APLL1 is in free-run mode or holdover mode, the VCBO frequency offset ppm value can introduce a similar frequency offset APLL2 outputs even though DPLL2 can stay in locked status. In this configuration example, verify that DPLL1 and APLL1 are locked first, toggle PLL2 enable cycle (APLLx_EN bit = 0 → 1) to calibrate VCO2, and then double check PLL2 lock status.

In above example, APLL1 is the upstream PLL, while APLL2 is the downstream PLL. If there are system start-up requirements on the clock sequencing, APLL2 also can be configured as the upstream PLL.

When cascading PLLs, the downstream APLL can use the DPLL or bypass and power down the DPLL depending on performance requirements. If DPLL2 is disabled from above APLL cascaded mode, then DPLL1-only cascade mode can be used (Figure 7-6). In this case, VCO2 can track the VCO1 domain during DPLL1 lock acquisition and locked modes, allowing the clock domain of APLL2 to be synchronized to the DPLL1 reference input.

When a DPLL is disabled, using the 24-bit numerator and programmable 24-bit denominator is recommended instead of the fixed 40-bit denominator to eliminate frequency error from APLL reference to output.

Do not cascade one VCO output to both the DPLL reference and APLL reference of the same DPLL/APLL pair.

Figure 7-5 APLL Cascaded With DPLLs Enabled Example

Figure 7-6 APLL Cascaded With DPLL Disabled Example