SNAS834 November   2024 LMK5C22212A

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
    2. 6.2 Output Clock Test Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 PLL Architecture Overview
      2. 7.2.2 DPLL
        1. 7.2.2.1 Independent DPLL Operation
        2. 7.2.2.2 Cascaded DPLL Operation
        3. 7.2.2.3 APLL Cascaded With DPLL
      3. 7.2.3 APLL-Only Mode
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Input (XO)
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Clock Input Interfacing and Termination
      4. 7.3.4  Reference Input Mux Selection
        1. 7.3.4.1 Automatic Input Selection
        2. 7.3.4.2 Manual Input Selection
      5. 7.3.5  Hitless Switching
        1. 7.3.5.1 Hitless Switching With Phase Cancellation
        2. 7.3.5.2 Hitless Switching With Phase Slew Control
      6. 7.3.6  Gapped Clock Support on Reference Inputs
      7. 7.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 7.3.7.1 XO Input Monitoring
        2. 7.3.7.2 Reference Input Monitoring
          1. 7.3.7.2.1 Reference Validation Timer
          2. 7.3.7.2.2 Frequency Monitoring
          3. 7.3.7.2.3 Missing Pulse Monitor (Late Detect)
          4. 7.3.7.2.4 Runt Pulse Monitor (Early Detect)
          5. 7.3.7.2.5 Phase Valid Monitor for 1-PPS Inputs
        3. 7.3.7.3 PLL Lock Detectors
        4. 7.3.7.4 Tuning Word History
        5. 7.3.7.5 Status Outputs
        6. 7.3.7.6 Interrupt
      8. 7.3.8  PLL Relationships
        1. 7.3.8.1  PLL Frequency Relationships
          1. 7.3.8.1.1 APLL Phase Frequency Detector (PFD) and Charge Pump
          2. 7.3.8.1.2 APLL VCO Frequency
          3. 7.3.8.1.3 DPLL TDC Frequency
          4. 7.3.8.1.4 DPLL VCO Frequency
          5. 7.3.8.1.5 Clock Output Frequency
        2. 7.3.8.2  Analog PLLs (APLL1, APLL2)
        3. 7.3.8.3  APLL Reference Paths
          1. 7.3.8.3.1 APLL XO Doubler
          2. 7.3.8.3.2 APLL XO Reference (R) Divider
        4. 7.3.8.4  APLL Feedback Divider Paths
          1. 7.3.8.4.1 APLL N Divider With Sigma-Delta Modulator (SDM)
        5. 7.3.8.5  APLL Loop Filters (LF1, LF2)
        6. 7.3.8.6  APLL Voltage-Controlled Oscillators (VCO1, VCO2)
          1. 7.3.8.6.1 VCO Calibration
        7. 7.3.8.7  APLL VCO Clock Distribution Paths
        8. 7.3.8.8  DPLL Reference (R) Divider Paths
        9. 7.3.8.9  DPLL Time-to-Digital Converter (TDC)
        10. 7.3.8.10 DPLL Loop Filter (DLF)
        11. 7.3.8.11 DPLL Feedback (FB) Divider Path
      9. 7.3.9  Output Clock Distribution
      10. 7.3.10 Output Source Muxes
      11. 7.3.11 Output Channel Muxes
      12. 7.3.12 Output Dividers (OD)
      13. 7.3.13 Output Delay
      14. 7.3.14 Clock Outputs
        1. 7.3.14.1 Differential Output
        2. 7.3.14.2 LVCMOS Output
        3. 7.3.14.3 SYSREF/1PPS Output
      15. 7.3.15 Output Auto-Mute During LOL
      16. 7.3.16 Glitchless Output Clock Start-Up
      17. 7.3.17 Clock Output Interfacing and Termination
      18. 7.3.18 Output Synchronization (SYNC)
      19. 7.3.19 Zero-Delay Mode (ZDM)
      20. 7.3.20 DPLL Programmable Phase Delay
      21. 7.3.21 Time Elapsed Counter (TEC)
        1. 7.3.21.1 Configuring TEC Functionality
        2. 7.3.21.2 SPI as a Trigger Source
        3. 7.3.21.3 GPIO Pin as a TEC Trigger Source
          1. 7.3.21.3.1 An Example: Making a Time Elapsed Measurement Using TEC and GPIO1 as Trigger
        4. 7.3.21.4 Other TEC Behavior
    4. 7.4 Device Functional Modes
      1. 7.4.1 DPLL Operating States
        1. 7.4.1.1 Free-Run
        2. 7.4.1.2 Lock Acquisition
        3. 7.4.1.3 DPLL Locked
        4. 7.4.1.4 Holdover
      2. 7.4.2 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
        1. 7.4.2.1 DPLL DCO Control
        2. 7.4.2.2 DPLL DCO Relative Adjustment Frequency Step Size
        3. 7.4.2.3 APLL DCO Frequency Step Size
      3. 7.4.3 APLL Frequency Control
      4. 7.4.4 Device Start-Up
        1. 7.4.4.1 Device Power-On Reset (POR)
        2. 7.4.4.2 PLL Start-Up Sequence
        3. 7.4.4.3 Start-Up Options for Register Configuration
        4. 7.4.4.4 GPIO1 and SCS_ADD Functionalities
        5. 7.4.4.5 ROM Page Selection
        6. 7.4.4.6 EEPROM Overlay
      5. 7.4.5 Programming
        1. 7.4.5.1 Memory Overview
        2. 7.4.5.2 Interface and Control
          1. 7.4.5.2.1 Programming Through TICS Pro
          2. 7.4.5.2.2 SPI Serial Interface
          3. 7.4.5.2.3 I2C Serial Interface
        3. 7.4.5.3 General Register Programming Sequence
        4. 7.4.5.4 Steps to Program the EEPROM
          1. 7.4.5.4.1 Overview of the SRAM Programming Methods
          2. 7.4.5.4.2 EEPROM Programming With the Register Commit Method
          3. 7.4.5.4.3 EEPROM Programming With the Direct Writes Method or Mixed Method
          4. 7.4.5.4.4 Five MSBs of the I2C Address and the EEPROM Revision Number
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Start-Up Sequence
      2. 8.1.2 Power Down (PD#) Pin
      3. 8.1.3 Strap Pins for Start-Up
      4. 8.1.4 Pin States
      5. 8.1.5 ROM and EEPROM
      6. 8.1.6 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 8.1.6.1 Power-On Reset (POR) Circuit
        2. 8.1.6.2 Power Up From a Single-Supply Rail
        3. 8.1.6.3 Power Up From Split-Supply Rails
        4. 8.1.6.4 Non-Monotonic or Slow Power-Up Supply Ramp
      7. 8.1.7 Slow or Delayed XO Start-Up
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Supply Bypassing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Thermal Reliability
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Glossary
    6. 9.6 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 LMK5C22212A RGC Package 64-Pin VQFN Top View
Table 4-1 LMK5C22212A Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
POWER
VDDO_0_11PPower supply for OUT0 and OUT1. Connect to supply; do not leave floating or connect to GND.
VDD_XO8PPower supply for XO. Connect to supply; do not leave floating or connect to GND.
VDDO_2_311PPower supply for OUT2 and OUT3. Connect to supply; do not leave floating or connect to GND.
VDD_APLL223PPower supply for APLL2
VDDO_4_To_728PPower supply for OUT4 to OUT7
VDD_IN033PPower supply for IN0 DPLL reference
VDD_IN137PPower supply for IN1 DPLL reference
VDD_DIG41PPower supply for digital
VDD_DIG44pPower supply for digital. Typically connected to pin 41.
VDD_APLL147PPower supply for APLL1. Connect to supply; do not leave floating or connect to GND.
VDDO_8_TO_1155PPower supply for OUT8 to OUT11.
DAPN/AGGround
LF219AExternal loop filter cap for APLL2 (100nF), refer to APLL Loop Filters (LF1, LF2) for more details.
CAP3_APLL220AInternal bias bypass capacitor for APLL2 VCO (10µF)
CAP2_APLL221AInternal bias bypass capacitor for APLL2 VCO (10µF)
CAP1_APLL222ALDO bypass capacitor for APLL2 VCO (10µF)
CAP_DIG40ALDO bypass capacitor for Digital Core Logic (100nF)
CAP_APLL148AInternal bias bypass capacitor for APLL1 (10µF)
LF149AExternal loop filter cap for APLL1 (470nF), refer to APLL Loop Filters (LF1, LF2) for more details.
XO9IXO/TCXO/OCXO input pin, refer to Oscillator Input (XO) for configuring the internal XO input termination.
IN0_P34IReference input to DPLLx or buffered to OUT0 or OUT1. Refer to Reference Inputs for configuring the internal reference input termination.
IN0_N35I
IN1_P39IReference input to DPLLx or buffered to OUT0 or OUT1. Refer to Reference Inputs for configuring the internal reference input termination.
IN1_N38I
OUT0_P2OClock Output 0. Sources from DPLL reference inputs, XO, or all VCO post-dividers. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, HCSL, 1.8V LVCMOS, or 2.65V LVCMOS. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT0_N3O
OUT1_N4OClock Output 1. Sources from DPLL reference inputs, XO, or all VCO post-dividers. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS, HCSL, 1.8V LVCMOS, or 2.65V LVCMOS. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT1_P5O
OUT2_P12OClock Output 2. Sources from APLL1 and APLL2. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT2_N13O
OUT3_N14OClock Output 3. Sources from APLL1 and APLL2. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT3_P15O
OUT4_P26OClock Output 4. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT4_N27O
OUT5_P24OClock Output 5. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT5_N25O
OUT6_P29OClock Output 6. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT6_N30O
OUT7_N31OClock Output 7. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT7_P32O
OUT8_P51OClock Output 8. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT8_N52O
OUT9_N53OClock Output 9. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT9_P54O
OUT10_P56OClock Output 10. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT10_N57O
OUT11_N58OClock Output 11. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on configuring and terminating the outputs.
OUT11_P59O
GPIO2(2)10I/O, SPOR: See ROM Page Selection
Normal Operation: GPIO input or output
SDIO(3)16I/OSPI or I2C Data (SDA)
SCK(3)17ISPI or I2C Clock (SCL)
SCS_ADD(2)18I, SPOR: I2C address select (see GPIO1 and SCS_ADD Functionalities and I2C Serial Interface)
Normal Operation: SPI Chip Select (2-state)
PD# 36IDevice power down (active low), internal 200kΩ pullup to VCC
GPIO0(2)50I/O, SPOR: See ROM Page Selection
Normal Operation: GPIO input or output
GPIO1(2)64I/O, SPOR: See GPIO1 and SCS_ADD Functionalities
Normal Operation: GPIO input or output
NC6-No connect. Leave floating, do not connect to GND.
NC7
NC60
NC61-
NC62
NC63-
NC42-No connect. Leave floating or connect to GND.
NC43-
NC45-
NC46-
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input or Output, A = Analog, S = Configuration.
(2) When 3-level mode is enabled during power supply ramp or when PD# is LOW: internal voltage divider of 555kΩ to VCC and 201kΩ to GND. When 2 level input mode is enabled: internal 408kΩ pulldown to GND.
(3) 670kΩ pullup to internal 2.6V LDO.