SBOS671D September   2018  – December 2022 OPA2828 , OPA828

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Phase-Reversal Protection
      2. 7.3.2  Electrical Overstress
      3. 7.3.3  MUX Friendly Inputs
      4. 7.3.4  Overload Power Limiter
      5. 7.3.5  Noise Performance
        1. 7.3.5.1 Low Noise
      6. 7.3.6  Capacitive Load and Stability
      7. 7.3.7  Settling Time
      8. 7.3.8  Slew Rate
      9. 7.3.9  Full-Power Bandwidth
      10. 7.3.10 Small-Signal Response
      11. 7.3.11 Thermal Shutdown
      12. 7.3.12 Low Offset Voltage Drift
      13. 7.3.13 Overload Recovery
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 SAR ADC Driver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Low-Pass Filter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
        2. 8.4.1.2 PowerPAD™ Design Considerations (DGN package only)
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 Filter Design Tool
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Typical Characteristics

At TA = 25°C, RL = 2 kΩ connected to midsupply, and VCM = VOUT = midsupply, and VS = ±18 V (unless otherwise noted)

Table 6-1 Table of Graphs
DESCRIPTIONFIGURE
Input Voltage Noise Density vs FrequencyFigure 6-1
. Integrated Input Voltage Noise vs BandwidthFigure 6-2
Total Harmonic Distortion + Noise Ratio vs FrequencyFigure 6-3
Total Harmonic Distortion + Noise Ratio vs Output AmplitudeFigure 6-4
. 0.1-Hz To 10-Hz NoiseFigure 6-5
Offset Voltage Production DistributionFigure 6-6, Figure 6-7
Offset Voltage Drift Production DistributionFigure 6-8, Figure 6-9
Offset Voltage vs Common-Mode VoltageFigure 6-10
Offset Voltage vs Power Supply VoltageFigure 6-11
Offset Voltage vs Output VoltageFigure 6-12
. Offset Voltage vs TemperatureFigure 6-13
Input Bias and Input Offset Current vs Common-Mode VoltageFigure 6-14
Input Bias and Input Offset Current vs TemperatureFigure 6-15
Quiescent Current vs Output VoltageFigure 6-16
Quiescent Current vs TemperatureFigure 6-17
Output Voltage Swing vs Output Sourcing CurrentFigure 6-18
Output Voltage Swing vs Output Sinking CurrentFigure 6-19
Power-Supply Rejection Ratio vs FrequencyFigure 6-20
Common-Mode Rejection Ratio vs FrequencyFigure 6-21
Power-Supply Rejection Ratio vs TemperatureFigure 6-22
Common-Mode Rejection Ratio vs TemperatureFigure 6-23
Open-Loop Gain and Phase vs FrequencyFigure 6-24
Closed-Loop Gain vs FrequencyFigure 6-25
Open-Loop Gain vs TemperatureFigure 6-26
Open-Loop Output Impedance vs FrequencyFigure 6-27
Small-Signal Overshoot vs Capacitive Load, Gain = +1Figure 6-28
Small-Signal Overshoot vs Capacitive Load, Gain = –1Figure 6-29
No Phase ReversalFigure 6-30
Positive Overload RecoveryFigure 6-31
Negative Overload RecoveryFigure 6-32
. Small-Signal Step ResponseFigure 6-33
Large-Signal Step ResponseFigure 6-34
12-bit, 14-bit Settling TimeFigure 6-35, Figure 6-36
Short-Circuit Current vs TemperatureFigure 6-37
Slew Rate vs TemperatureFigure 6-38
Slew Rate vs Output Step SizeFigure 6-39
Maximum Output Voltage vs FrequencyFigure 6-40
Intermodulation DistortionFigure 6-41
Electromagnetic Interference RejectionFigure 6-42
Harmonic Distortion vs FrequencyFigure 6-43
Channel Separation Figure 6-44
GUID-37F57C14-3F88-4D31-9B29-116CCFB3883A-low.gif
 
Figure 6-1 Input Voltage Noise Density vs Frequency
 
Figure 6-3 Total Harmonic Distortion + Noise Ratio vs Frequency
 
Figure 6-5 0.1-Hz To 10-Hz Noise
DGN package, VS = ±15 V
Figure 6-7 Offset Voltage Production Distribution
DGN package, TA = –40°C to +125°C
Figure 6-9 Offset Voltage Drift Production Distribution
5 typical units
Figure 6-11 Offset Voltage vs Power Supply Voltage
 
Figure 6-13 Offset Voltage vs Temperature
 
Figure 6-15 Input Bias and Input Offset Current vs Temperature
 
Figure 6-17 Quiescent Current vs Temperature
VS = ±15 V
Figure 6-19 Output Voltage Swing vs Output Sinking Current
Differential amp configuration, 10-kΩ resistors
Figure 6-21 Common-Mode Rejection Ratio vs Frequency
GUID-54D2D662-4312-4FCB-81AB-BCAFBA03A362-low.gif
 
 
Figure 6-23 Common-Mode Rejection Ratio vs Temperature
 
Figure 6-25 Closed-Loop Gain vs Frequency
 
Figure 6-27 Open-Loop Output Impedance vs Frequency
GUID-32E030F7-BA29-4C6C-9D5F-ED873CE633D1-low.gif
Gain = –1
Figure 6-29 Small-Signal Overshoot vs Capacitive Load
 
Figure 6-31 Positive Overload Recovery
 
Figure 6-33 Small-Signal Step Response
GUID-6F63C7EE-B86A-4945-B764-C3EEB230E2D6-low.gif
 
Figure 6-35 12-bit Settling Time
 
Figure 6-37 Short-Circuit Current vs Temperature
Buffer configuration
Figure 6-39 Slew Rate vs Output Step Size
 
Figure 6-41 Intermodulation Distortion
 
Figure 6-43 Harmonic Distortion vs Frequency
Noise bandwidth = 0.1 Hz to indicated frequency
Figure 6-2 Integrated Input Voltage Noise vs Bandwidth
 
Figure 6-4 Total Harmonic Distortion + Noise Ratio vs Output Amplitude
VS = ±15 V
Figure 6-6 Offset Voltage Production Distribution
TA = –40°C to +125°C
Figure 6-8 Offset Voltage Drift Production Distribution
VS = ±15 V, 5 typical units
Figure 6-10 Offset Voltage vs Common-Mode Voltage
VS = ±15 V, 5 typical units
Figure 6-12 Offset Voltage vs Output Voltage
 
Figure 6-14 Input Bias and Input Offset Current vs Common-Mode Voltage
 
Figure 6-16 Quiescent Current vs Supply Voltage
VS = ±15 V
Figure 6-18 Output Voltage Swing vs Output Sourcing Current
 
Figure 6-20 Power-Supply Rejection Ratio vs Frequency
GUID-A2463D21-066A-4BAA-A3D2-59B394B88991-low.gif
 
Figure 6-22 Power-Supply Rejection Ratio vs Temperature
 
 
Figure 6-24 Open-Loop Gain and Phase vs Frequency
 
Figure 6-26 Open-Loop Gain vs Temperature
GUID-AC354280-F0CB-4575-8E7C-0C1959F84790-low.gif
Gain = +1
Figure 6-28 Small-Signal Overshoot vs Capacitive Load
GUID-472FEB3C-16D4-48BD-A663-DDF75FDFF121-low.gif
Gain = +1
Figure 6-30 No Phase Reversal
GUID-518C10AA-1D1D-4196-B549-568BDEDE3D7E-low.gif
 
Figure 6-32 Negative Overload Recovery
 
 
Figure 6-34 Large-Signal Step Response
GUID-D9001E16-57B9-4165-8449-22598FB2D42B-low.gif
 
Figure 6-36 14-bit Settling Time
 
Figure 6-38 Slew Rate vs Temperature
 
Figure 6-40 Maximum Output Voltage vs Frequency
GUID-CB5C39C2-0550-4159-9614-6E759A44FDC7-low.gif
 
 
Figure 6-42 Electromagnetic Interference Rejection
OPA2828, DGN package
Figure 6-44 Channel Separation