SBOS263H October   2002  – December 2024 OPA830

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configurations
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics for D Package VS = ±5V
    6. 6.6  Electrical Characteristics for D Package VS = 5V
    7. 6.7  Electrical Characteristics for D Package VS = 3V
    8. 6.8  Electrical Characteristics for DBV Package VS = ±5V
    9. 6.9  Electrical Characteristics for DBV Package VS = 5V
    10. 6.10 Electrical Characteristics for DBV Package VS = 3V
    11. 6.11 Typical Characteristics: VS = ±5V
    12. 6.12 Typical Characteristics: VS = ±5V, Differential Configuration
    13. 6.13 Typical Characteristics: VS = 5V
    14. 6.14 Typical Characteristics: VS = 5V, Differential Configuration
    15. 6.15 Typical Characteristics: VS = 3V
    16. 6.16 Typical Characteristics: VS = 3V, Differential Configuration
  8. 7 Parameter Measurement Information
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Wideband Voltage-Feedback Operation
      2. 8.1.2  DC Level-Shifting
      3. 8.1.3  Optimizing Resistor Values
      4. 8.1.4  Bandwidth Versus Gain: Noninverting Operation
      5. 8.1.5  Inverting Amplifier Operation
      6. 8.1.6  Output Current and Voltages
      7. 8.1.7  Driving Capacitive Loads
      8. 8.1.8  Distortion Performance
      9. 8.1.9  Noise Performance
      10. 8.1.10 DC Accuracy and Offset Control
      11. 8.1.11 Thermal Analysis
    2. 8.2 Typical Applications
      1. 8.2.1 Single-Supply ADC Interface
      2. 8.2.2 AC-Coupled Output Video Line Driver
      3. 8.2.3 Noninverting Amplifier With Reduced Peaking
      4. 8.2.4 Single-Supply Active Filter
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 Input and ESD Protection
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Demonstration Boards
        2. 9.1.1.2 Macromodel and Applications Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.3 Optimizing Resistor Values

The OPA830 is a unity-gain stable, voltage-feedback op amp; therefore, a wide range of resistor values can be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting, unity-gain follower application, make the feedback connection with a direct short.

At less than 200Ω, the feedback network presents additional output loading that can degrade the harmonic distortion performance of the OPA830. At greater than 1kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor can cause unintentional band limiting in the amplifier response.

A good practice is to target the parallel combination of RF and RG (see also Figure 8-3) to be less than approximately 400Ω. The combined impedance of RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network, and thus a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 400Ω keeps this pole greater than 200MHz. Independently, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This increase is acceptable if the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest.

In the inverting configuration, be aware of an additional design consideration: RG becomes the input resistor, and therefore, the load impedance to the driving source. If impedance matching is desired, RG can be set equal to the required termination value. However, at low inverting gains, the resulting feedback resistor value can present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50Ω input matching resistor (= RG) requires a 100Ω feedback resistor, which contributes to output loading in parallel with the external load. In such a case, increase both the RF and RG values, and then achieve the input matching impedance with a third resistor to ground (see Figure 8-5). The total input impedance becomes the parallel combination of RG and the additional shunt resistor.