The device supports the I2C control protocol as a slave device, and is capable of operating in standard mode, fast mode, and fast mode plus. The I2C control protocol requires a 7-bit slave address. The five most significant bits (MSBs) of the slave address are fixed at 10010 and cannot be changed. The two least significant bits (LSBs) are programmable and are controlled by the ADDR0_SCLK and ADDR1_MISO pins. These two pins must always be either pulled to VSS or IOVDD. If the I2C_BRDCAST_EN (P0_R2_D2) bit is set to 1'b1, then the I2C slave address is fixed to 1001000 in order to allow simultaneous I2C broadcast communication to all PCM6xx0-Q1 devices in the system. Table 49 lists the four possible device addresses resulting from this configuration.
|ADDR1_MISO||ADDR0_SCLK||I2C_BRDCAST_EN (P0_R2_D2)||I2C SLAVE ADDRESS|
|0||0||0 (default)||1001 000|
|0||1||0 (default)||1001 001|
|1||0||0 (default)||1001 010|
|1||1||0 (default)||1001 011|