The PCM6x60-Q1 consist of six pairs and the PCM6x40-Q1 consist of four pairs of analog input pins (INxP and INxM) that can be configured as either differential or single-ended inputs for the recording channel. These devices support simultaneous recording of up to six channels in the PCM6x60-Q1 and four channels in the PCM6x40-Q1 using the multichannel ADC. The input source for the analog pins can be either analog microphones or line, aux inputs from the system board. Table 8 describes how to set the input configuration for the record channel.
|P0_R60_D[6:5] : CH1_INSRC[1:0]||INPUT CHANNEL 1 RECORD SOURCE SELECTION|
|00 (default)||Analog differential input for channel 1|
|01||Analog single-ended input for channel 1|
|10 or 11||Reserved (do not use this setting)|
Similarly, the input source selection setting for input channel 2 to channel 6 can be configured using the CH2_INSRC[1:0] (P0_R65_D[6:5]) to CH6_INSRC[1:0] (P0_R85_D[6:5]) registers bits, respectively.
The device supports the input DC fault diagnostic feature for microphone recording with the DC-coupled inputs configuration; however, the device also supports an option for AC-coupled inputs if the DC diagnostic is not required for the specific input pins. This configuration can be done independently for each channel by setting the CH1_DC (P0_R60_D4) to CH6_DC (P0_R85_D4) register bits.
For the DC-coupled line input configuration, the DC common-mode difference (INxP – INxM) for the analog input pins must be 0 V to support the 10-VRMS full-scale differential input. For the DC-coupled microphone input configuration, the DC common-mode difference (INxP – INxM) for the analog input pins must be within 3.4 V to 5.0 V to support the 2-VRMS full-scale differential input in the default mode of operation. Alternatively, the device has a mode to support more than a 2-VRMS differential DC-coupled microphone signal by setting the CH1_MIC_IN_RANGE, P0_R60_D3, register bit for channel 1 and, similarly, the CH2_MIC_IN_RANGE, P0_R65_D3 to CH6_MIC_IN_RANGE, P0_R85_D3 registers bit (respectively) for channels 2 to 6. If the CH1_MIC_IN_RANGE bit is set high (the recommended setting to support a higher DC common-mode difference and a higher AC signal swing), then the device supports the maximum differential input voltage IN1P–IN1M as high as 8.4 V (for the MICBIAS 9-V setting), including the AC signal and DC differential common-mode voltage. The DC differential common-mode voltage is later filtered out by the digital high-pass filter and the digital output full-scale corresponds to the 10-VRMS AC signal in this case.
Figure 37 and Figure 38 show how to connect a DC-coupled microphone for a differential and single-ended input, respectively. The value of the external bias resistor, R1, must be appropriately chosen based upon the microphone impedance. For a differential input, the value of the external bias resistor is recommended to be used for half of the microphone impedance, whereas for a single-ended input, the external bias resistor is recommended to be the same as the microphone impedance.
In AC-coupled mode, the value of the coupling capacitor must be so chosen that the high-pass filter formed by the coupling capacitor and the input impedance do not affect the signal content. At power-up, before proper recording can begin, this coupling capacitor must be charged up to the common-mode voltage. For single-ended input configuration, the INxM pin must be grounded after the AC coupling capacitor in AC-coupled mode.
Figure 39 and Figure 40 show how to connect an AC-coupled microphone or line source for a differential and single-ended input, respectively. In AC-coupled mode, the device input pins INxP and INxM, must be biased appropriately for the DC common-mode value either using the on-chip MICBIAS output voltage along with external bias resistor, R0, or using an external bias generator circuit. The maximum value for resistor R0 depends upon the signal swing and the MICBIAS value programmed. See the PCM6xx0-Q1 AC Coupled External Resistor Calculator to calculate the R0 value for the desired system configuration.