This register is the ASI master mode configuration register 0.
|7||MST_SLV_CFG||RW||0h||ASI master or slave configuration register setting.
0d = Device is in slave mode (both BCLK and FSYNC are inputs to the device)
1d = Device is in master mode (both BCLK and FSYNC are generated from the device)
|6||AUTO_CLK_CFG||RW||0h||Automatic clock configuration setting.
0d = Auto clock configuration is enabled (all internal clock divider and PLL configurations are auto derived)
1d = Auto clock configuration is disabled (custom mode and device GUI must be used for the device configuration settings)
|5||AUTO_MODE_PLL_DIS||RW||0h||Automatic mode PLL setting.
0d = PLL is enabled in auto clock configuration
1d = PLL is disabled in auto clock configuration
|4||BCLK_FSYNC_GATE||RW||0h||BCLK and FSYNC clock gate (valid when the device is in master mode).
0d = Do not gate BCLK and FSYNC
1d = Force gate BCLK and FSYNC when being transmitted from the device in master mode
|3||FS_MODE||RW||0h||Sample rate setting (valid when the device is in master mode).
0d = fS is a multiple (or submultiple) of 48 kHz
1d = fS is a multiple (or submultiple) of 44.1 kHz
|2-0||MCLK_FREQ_SEL[2:0]||RW||2h||These bits select the MCLK (GPIO or GPIx) frequency for the PLL source clock input (valid when the device is in master mode and MCLK_FREQ_SEL_MODE = 0).
0d = 12 MHz
1d = 12.288 MHz
2d = 13 MHz
3d = 16 MHz
4d = 19.2 MHz
5d = 19.68 MHz
6d = 24 MHz
7d = 24.576 MHz