This regiser is the interrupt configuration register.
0d = Active low (IRQZ)
1d = Active high (IRQ)
|6-5||INT_EVENT[1:0]||RW||0h||Interrupt event configuration.
0d = INT asserts on any unmasked latched interrupts event
1d = Reserved
2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any unmasked latched interrupts event
3d = INT asserts for 2 ms (typical) one time on each pulse for any unmasked interrupts event
|4-3||PD_ON_FLT_CFG[1:0]||RW||0h||Powerdown configuration when fault detected for any channel or MICBIAS fault detected.
0d = Faults event are not used for ADC and MICBIAS power down. It is recommend to set these bits as 2d to shutdown the blocks for which fault occurred.
1d = Only unmasked faults are used for power down of respective ADC channel; In case of MICBIAS fault detected, MICBIAS and all ADC channels gets powered-down based on P0_R58 settings
2d = Both masked or unmasked faults are used for power down of respective ADC channel; In case of MICBIAS fault detected, MICBIAS and all ADC channels gets powered-down based on P0_R58 settings.
3d = Reserved
|2||LTCH_READ_CFG||RW||0h||Interrupt latch registers readback configuration.
0d = All interrupts can be read through the LTCH registers
1d = Only unmasked interrupts can be read through the LTCH registers
|1||PD_ON_FLT_RCV_CFG||RW||0h||Recovery configuration for ADC channels when fault goes away.
0d = Auto recovery, ADC channels are re-powered up when fault goes away
1d = Manual recovery, ADC channels are required to power-up manually using P0_R119 when fault goes away
|0||LTCH_CLR_ON_READ||RW||0h||Configuration for clearing LTCH register bits.
0d = LTCH register bits are cleared on register read only if live status is zero
1d = LTCH register bits are cleared on register read irrespective of live status and set only if live status goes again low to high