Refer to the PDF data sheet for device specific package drawings
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The TPS65917 PMIC LDOLN output or LDO0 on LP8733Q dual power solution is specifically designed to meet this low noise requirement.
For more information about Input Voltage Sources, see DPLLs, DLLs Specifications
Table 8-6 presents the voltage inputs that supply the DPLLs.
|vdda_per||DPLL_PER and PER HSDIVIDER analog power supply|
|vdda_ddr_dsp||DPLL_EVE_VID_DSP, DPLL_DDR and DDR HSDIVIDER analog power supply|
|vdda_gmac_core||GMAC PLL, GMAC HSDIVIDER, DPLL_CORE and CORE HSDIVIDER analog power supply|