6.2 DPLLs, DLLs Specifications
For more information, see:
- Power, Reset, and Clock Management / Clock Management Functional Description / Internal Clock Sources / Generators / Generic DPLL Overview Section
- Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the PRCM module.
- They have their own independent power domain (each one embeds its own switch and can be controlled as an independent functional power domain)
- They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
- DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
- DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock , a 96-MHz functional clock to subsystems and peripherals.
- DPLL_GMAC_DSP: It supplies RGMII, EVE1 and DSP0 module functional clocks.
- DPLL_EVE_VID_DSP: It provides a few module functional clocks (EVE_GFCLK, VID_PIX_CLK and DSP1_CLK).
- DPLL_DDR: It generates clocks for the one External Memory Interface (EMIF) controller and its associated EMIF PHYs.
The following DPLLs are controlled by the clock manager located in the always-on Core power domain (CM_CORE_AON):
- DPLL_CORE, DPLL_DDR, DPLL_GMAC_DSP, DPLL_PER, DPLL_EVE_VID_DSP.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and Clock Management (PRCM) chapter of the Device TRM.