22.214.171.124 If QSPI is operated in Mode 3 (POL=1, PHA=1):
- The qspi1_rtclk input can be left unconnected.
- The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be approximately equal to the signal propagation delay of the control and data signals between the QSPI device and the SoC device (E to F, or F to E).
- The signal propagation delay from the qspi1_sclk signal to the QSPI device CLK pin (A to C) must be < 450pS (~7cm as stripline or ~8cm as microstrip).
- 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-20.
- Propagation delays and matching:
- A to C = E to F.
- Matching skew: < 60Ps
- A to B < 450pS
Figure 8-20 QSPI Interface High Level Schematic Mode 3 (POL=1, PHA=1)
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-tuning if needed.