SBOS891B October   2018  – April 2021 TMP144

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 UART Interface Timing
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Up
      2. 7.3.2 Digital Temperature Output
      3. 7.3.3 Timeout Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conversion Mode
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 One-Shot Mode
      4. 7.4.4 Extended Temperature Mode
      5. 7.4.5 Temperature Alert Function
      6. 7.4.6 Interrupt Functionality
    5. 7.5 SMAART Wire / UART Interface
      1. 7.5.1 Communication Protocol
      2. 7.5.2 Global Software Reset
      3. 7.5.3 Global Initialization and Address Assignment Sequence
      4. 7.5.4 Global Clear Interrupt
      5. 7.5.5 Global Read and Write
      6. 7.5.6 Individual Read and Write
    6. 7.6 Register Maps
      1. 7.6.1 Temperature Result Register (P[1:0] = 00) [reset = 0000h]
      2. 7.6.2 Configuration Register (P[1:0] = 01) [reset = 0200h]
      3. 7.6.3 Temperature Low Limit Register (P[1:0] = 10) [reset = F600h]
      4. 7.6.4 Temperature High Limit Register (P[1:0] = 11) [reset = 3C00h]
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Trace Length
        2. 8.2.2.2 Voltage Drop Effect
        3. 8.2.2.3 Power Supply Noise Filtering
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Communication Protocol

Each communication of the SMAART Wire™ / UART protocol consists of 8-bit word, transferred least significant bit (LSB) first. Each 8-bit word begins with a Start bit that is logic low, and ends with a Stop bit that is logic high. By using a Start bit and Stop bit for each 8-bit word, the TMP144 can calibrate each word and keep synchronous communication throughout the process.

The steps for the SMAART Wire™ / UART communication protocol are:

  1. The host sends a Start bit to start the communication process.
  2. The host sends the calibration byte (55h) to allow the TMP144 to sync to the baud rate of the host.
  3. The host sends a Stop bit after the calibration byte.
  4. The host sends a second Start bit, followed by the command register byte and a Stop bit.
  5. The host sends a third Start bit, followed by the data byte only for writes.
  6. The host will send the data byte(s) if the instruction is a write command.
  7. The host sends a Stop bit to finish the process.
    Note: The device will break the chain and send the data byte(s) if the instruction sent in the command register is a read command.

The sequence is shown in Figure 7-4.

GUID-20200819-CA0I-XFWK-GVSM-DBLH0BZPZTFQ-low.gifFigure 7-4 Generic Communication Write Bitstream.

GUID-20200819-CA0I-KPJ6-KR3W-4B1QDTVL9XZB-low.gifFigure 7-5 Generic Communication Read Bitstream

The command byte is decoded by the TMP144 to determine the format of the subsequent communication operation. Table 7-2 lists the command register byte values.

Table 7-2 Command Byte Value
COMMAND OPERATIONCOMMAND BYTE ENCODINGHEX VALUE
C7 (MSB)C6C5C4C3C2C1C0 (LSB)
GLBLIN3/ID3IN2/ID2IN1/ID1IN0/ID0P1P0R/W
Global software reset10110100B4
Global initialization100011008C
Global address assignment1001000090
Global clear interrupt10101001A9
Global write11110P1P00Based on P[1:0]
Global read11110P1P01Based on P[1:0]
Individual write0ID3ID2ID1ID0P1P00Based on ID[3:0] and P[1:0]
Individual read0ID3ID2ID1ID0P1P01Based on ID[3:0] and P[1:0]