SBOS891B October 2018 – April 2021 TMP144
The TMP144 interrupts the host by disconnecting the bus and issuing an interrupt request by holding the bus low if all of following conditions are met as shown in Figure 7-3.
The interrupt on the bus is latched regardless of the status of LC. Writing a 1 to INT_EN automatically sets the LC bit. The TMP144 holds the bus low until one of the following events happen:
Each of these events clears the INT_EN. The TMP144 does not issue future interrupts until the host writes sets the INT_EN in the configuration register to re-enable future interrupts.
In a system with enabled interrupts, it is possible for a TMP144 on the bus to issue an interrupt at the same time that the host starts a communication sequence. To avoid this scenario, TI recommends that the host should check the status on the receiving side of the bus after transmitting the calibration byte. If it is 1, then the host can continue with the communication. If it is 0, one of the TMP144 devices on the bus is issuing an alert and the host must transmit a Global Interrupt Clear command.