SBOS891B October   2018  – April 2021 TMP144

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 UART Interface Timing
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Up
      2. 7.3.2 Digital Temperature Output
      3. 7.3.3 Timeout Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conversion Mode
      2. 7.4.2 Shutdown Mode
      3. 7.4.3 One-Shot Mode
      4. 7.4.4 Extended Temperature Mode
      5. 7.4.5 Temperature Alert Function
      6. 7.4.6 Interrupt Functionality
    5. 7.5 SMAART Wire / UART Interface
      1. 7.5.1 Communication Protocol
      2. 7.5.2 Global Software Reset
      3. 7.5.3 Global Initialization and Address Assignment Sequence
      4. 7.5.4 Global Clear Interrupt
      5. 7.5.5 Global Read and Write
      6. 7.5.6 Individual Read and Write
    6. 7.6 Register Maps
      1. 7.6.1 Temperature Result Register (P[1:0] = 00) [reset = 0000h]
      2. 7.6.2 Configuration Register (P[1:0] = 01) [reset = 0200h]
      3. 7.6.3 Temperature Low Limit Register (P[1:0] = 10) [reset = F600h]
      4. 7.6.4 Temperature High Limit Register (P[1:0] = 11) [reset = 3C00h]
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Trace Length
        2. 8.2.2.2 Voltage Drop Effect
        3. 8.2.2.3 Power Supply Noise Filtering
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Interrupt Functionality

The TMP144 interrupts the host by disconnecting the bus and issuing an interrupt request by holding the bus low if all of following conditions are met as shown in Figure 7-3.

  • INT_EN in the configuration register is set to 1;
  • The temperature result of the last conversion is greater than the value in the temperature high limit register or less than the value in the temperature low limit register (also indicated by a 1 in either FH or FL, respectively);
  • The bus is logic high and idle for more than 28 ms.
GUID-20200819-CA0I-QDGP-MMD5-TSXMGWBH1NJS-low.gif Figure 7-3 TMP144 Daisy-Chain: Bus Status During an Interrupt Request (Logic Low) From Second Device

The interrupt on the bus is latched regardless of the status of LC. Writing a 1 to INT_EN automatically sets the LC bit. The TMP144 holds the bus low until one of the following events happen:

  • Global Interrupt Clear command is received.
  • Global Software Reset command is received.
  • A power-on reset event occurs.

Each of these events clears the INT_EN. The TMP144 does not issue future interrupts until the host writes sets the INT_EN in the configuration register to re-enable future interrupts.

In a system with enabled interrupts, it is possible for a TMP144 on the bus to issue an interrupt at the same time that the host starts a communication sequence. To avoid this scenario, TI recommends that the host should check the status on the receiving side of the bus after transmitting the calibration byte. If it is 1, then the host can continue with the communication. If it is 0, one of the TMP144 devices on the bus is issuing an alert and the host must transmit a Global Interrupt Clear command.