SPRSP45C March   2020  – April 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins Table
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 GPIO Input X-BAR
      4. 5.4.4 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5.     Supply Voltages
    6. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption
      2. 6.5.2 Operating Mode Test Description
      3. 6.5.3 Current Consumption Graphs
      4. 6.5.4 Reducing Current Consumption
        1. 6.5.4.1 Typical Current Reduction per Disabled Peripheral
    7. 6.6  Electrical Characteristics
    8. 6.7  Thermal Resistance Characteristics for PN Package
    9. 6.8  Thermal Resistance Characteristics for PM Package
    10. 6.9  Thermal Resistance Characteristics for PT Package
    11. 6.10 Thermal Design Considerations
    12. 6.11 System
      1. 6.11.1  Power Management Module (PMM)
        1. 6.11.1.1 Introduction
        2. 6.11.1.2 Overview
          1. 6.11.1.2.1 Power Rail Monitors
            1. 6.11.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.11.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.11.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.11.1.2.2 External Supervisor Usage
          3. 6.11.1.2.3 Delay Blocks
          4. 6.11.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
        3. 6.11.1.3 External Components
          1. 6.11.1.3.1 Decoupling Capacitors
            1. 6.11.1.3.1.1 VDDIO Decoupling
            2. 6.11.1.3.1.2 VDD Decoupling
        4. 6.11.1.4 Power Sequencing
          1. 6.11.1.4.1 Supply Pins Ganging
          2. 6.11.1.4.2 Signal Pins Power Sequence
          3. 6.11.1.4.3 Supply Pins Power Sequence
            1. 6.11.1.4.3.1 Internal VREG/VDD Mode Sequence
            2. 6.11.1.4.3.2 Supply Sequencing Summary and Effects of Violations
            3. 6.11.1.4.3.3 Supply Slew Rate
        5. 6.11.1.5 Power Management Module Electrical Data and Timing
          1. 6.11.1.5.1 Power Management Module Characteristics
          2. 6.11.1.5.2 Power Management Module Operating Conditions
      2. 6.11.2  Reset Timing
        1. 6.11.2.1 Reset Sources
        2. 6.11.2.2 Reset Electrical Data and Timing
          1. 6.11.2.2.1 Reset (XRSn) Timing Requirements
          2. 6.11.2.2.2 Reset (XRSn) Switching Characteristics
          3. 6.11.2.2.3 Reset Timing Diagrams
      3. 6.11.3  Clock Specifications
        1. 6.11.3.1 Clock Sources
        2. 6.11.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.11.3.2.1.1 Input Clock Frequency
            2. 6.11.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.11.3.2.1.3 X1 Timing Requirements
            4. 6.11.3.2.1.4 APLL Characteristics
            5. 6.11.3.2.1.5 XCLKOUT Switching Characteristics
            6. 6.11.3.2.1.6 Internal Clock Frequencies
        3. 6.11.3.3 Input Clocks and PLLs
        4. 6.11.3.4 XTAL Oscillator
          1. 6.11.3.4.1 Introduction
          2. 6.11.3.4.2 Overview
            1. 6.11.3.4.2.1 Electrical Oscillator
              1. 6.11.3.4.2.1.1 Modes of Operation
                1. 6.11.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.11.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.11.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.11.3.4.2.2 Quartz Crystal
            3. 6.11.3.4.2.3 GPIO Modes of Operation
          3. 6.11.3.4.3 Functional Operation
            1. 6.11.3.4.3.1 ESR – Effective Series Resistance
            2. 6.11.3.4.3.2 Rneg – Negative Resistance
            3. 6.11.3.4.3.3 Start-up Time
            4. 6.11.3.4.3.4 DL – Drive Level
          4. 6.11.3.4.4 How to Choose a Crystal
          5. 6.11.3.4.5 Testing
          6. 6.11.3.4.6 Common Problems and Debug Tips
          7. 6.11.3.4.7 Crystal Oscillator Specifications
            1. 6.11.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.11.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
        5. 6.11.3.5 Internal Oscillators
          1. 6.11.3.5.1 INTOSC Characteristics
      4. 6.11.4  Flash Parameters
      5. 6.11.5  RAM Specifications
      6. 6.11.6  ROM Specifications
      7. 6.11.7  Emulation/JTAG
        1. 6.11.7.1 JTAG Electrical Data and Timing
          1. 6.11.7.1.1 JTAG Timing Requirements
          2. 6.11.7.1.2 JTAG Switching Characteristics
          3. 6.11.7.1.3 JTAG Timing Diagram
        2. 6.11.7.2 cJTAG Electrical Data and Timing
          1. 6.11.7.2.1 cJTAG Timing Requirements
          2. 6.11.7.2.2 cJTAG Switching Characteristics
          3. 6.11.7.2.3 cJTAG Timing Diagram
      8. 6.11.8  GPIO Electrical Data and Timing
        1. 6.11.8.1 GPIO – Output Timing
          1. 6.11.8.1.1 General-Purpose Output Switching Characteristics
        2. 6.11.8.2 GPIO – Input Timing
          1. 6.11.8.2.1 General-Purpose Input Timing Requirements
          2. 6.11.8.2.2 Sampling Mode
        3. 6.11.8.3 Sampling Window Width for Input Signals
      9. 6.11.9  Interrupts
        1. 6.11.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.11.9.1.1 External Interrupt Timing Requirements
          2. 6.11.9.1.2 External Interrupt Switching Characteristics
          3. 6.11.9.1.3 External Interrupt Timing
      10. 6.11.10 Low-Power Modes
        1. 6.11.10.1 Clock-Gating Low-Power Modes
        2. 6.11.10.2 Low-Power Mode Wake-up Timing
          1. 6.11.10.2.1 IDLE Mode Timing Requirements
          2. 6.11.10.2.2 IDLE Mode Switching Characteristics
          3. 6.11.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.11.10.2.4 STANDBY Mode Timing Requirements
          5. 6.11.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.11.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.11.10.2.7 HALT Mode Timing Requirements
          8. 6.11.10.2.8 HALT Mode Switching Characteristics
          9. 6.11.10.2.9 HALT Entry and Exit Timing Diagram
    13. 6.12 Analog Peripherals
      1. 6.12.1 Analog Pins and Internal Connections
      2. 6.12.2 Analog Signal Descriptions
      3. 6.12.3 Analog-to-Digital Converter (ADC)
        1. 6.12.3.1 ADC Configurability
          1. 6.12.3.1.1 Signal Mode
        2. 6.12.3.2 ADC Electrical Data and Timing
          1. 6.12.3.2.1 ADC Operating Conditions
          2. 6.12.3.2.2 ADC Characteristics
          3. 6.12.3.2.3 ADC INL and DNL
          4. 6.12.3.2.4 ADC Input Model
          5. 6.12.3.2.5 ADC Timing Diagrams
      4. 6.12.4 Temperature Sensor
        1. 6.12.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.12.4.1.1 Temperature Sensor Characteristics
      5. 6.12.5 Comparator Subsystem (CMPSS)
        1. 6.12.5.1 CMPSS Electrical Data and Timing
          1. 6.12.5.1.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.12.5.1.2 CMPSS DAC Static Electrical Characteristics
          4. 6.12.5.1.3 CMPSS Illustrative Graphs
    14. 6.13 Control Peripherals
      1. 6.13.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.13.1.1 Control Peripherals Synchronization
        2. 6.13.1.2 ePWM Electrical Data and Timing
          1. 6.13.1.2.1 ePWM Timing Requirements
          2. 6.13.1.2.2 ePWM Switching Characteristics
          3. 6.13.1.2.3 Trip-Zone Input Timing
            1. 6.13.1.2.3.1 Trip-Zone Input Timing Requirements
        3. 6.13.1.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 6.13.1.3.1 External ADC Start-of-Conversion Switching Characteristics
      2. 6.13.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.13.2.1 HRPWM Electrical Data and Timing
          1. 6.13.2.1.1 High-Resolution PWM Characteristics
      3. 6.13.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 6.13.3.1 High-Resolution Capture (HRCAP)
        2. 6.13.3.2 eCAP and HRCAP Block Diagram
        3. 6.13.3.3 eCAP/HRCAP Synchronization
        4. 6.13.3.4 eCAP Electrical Data and Timing
          1. 6.13.3.4.1 eCAP Timing Requirements
          2. 6.13.3.4.2 eCAP Switching Characteristics
        5. 6.13.3.5 HRCAP Electrical Data and Timing
          1. 6.13.3.5.1 HRCAP Switching Characteristics
          2. 6.13.3.5.2 HRCAP Figure and Graph
      4. 6.13.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.13.4.1 eQEP Electrical Data and Timing
          1. 6.13.4.1.1 eQEP Timing Requirements
          2. 6.13.4.1.2 eQEP Switching Characteristics
    15. 6.14 Communications Peripherals
      1. 6.14.1 Controller Area Network (CAN)
      2. 6.14.2 Inter-Integrated Circuit (I2C)
        1. 6.14.2.1 I2C Electrical Data and Timing
          1. 6.14.2.1.1 I2C Timing Requirements
          2. 6.14.2.1.2 I2C Switching Characteristics
          3. 6.14.2.1.3 I2C Timing Diagram
      3. 6.14.3 Power Management Bus (PMBus) Interface
        1. 6.14.3.1 PMBus Electrical Data and Timing
          1. 6.14.3.1.1 PMBus Electrical Characteristics
          2. 6.14.3.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.14.3.1.3 PMBus Standard Mode Switching Characteristics
      4. 6.14.4 Serial Communications Interface (SCI)
      5. 6.14.5 Serial Peripheral Interface (SPI)
        1. 6.14.5.1 SPI Master Mode Timings
          1. 6.14.5.1.1 SPI Master Mode Timing Requirements
          2. 6.14.5.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
          3. 6.14.5.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          4. 6.14.5.1.4 SPI Master Mode Timing Diagrams
        2. 6.14.5.2 SPI Slave Mode Timings
          1. 6.14.5.2.1 SPI Slave Mode Timing Requirements
          2. 6.14.5.2.2 SPI Slave Mode Switching Characteristics
          3. 6.14.5.2.3 SPI Slave Mode Timing Diagrams
      6. 6.14.6 Local Interconnect Network (LIN)
      7. 6.14.7 Fast Serial Interface (FSI)
        1. 6.14.7.1 FSI Transmitter
          1. 6.14.7.1.1 FSITX Electrical Data and Timing
            1. 6.14.7.1.1.1 FSITX Switching Characteristics
            2. 6.14.7.1.1.2 FSITX Timings
        2. 6.14.7.2 FSI Receiver
          1. 6.14.7.2.1 FSIRX Electrical Data and Timing
            1. 6.14.7.2.1.1 FSIRX Timing Requirements
            2. 6.14.7.2.1.2 FSIRX Switching Characteristics
            3. 6.14.7.2.1.3 FSIRX Timings
        3. 6.14.7.3 FSI SPI Compatibility Mode
          1. 6.14.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.14.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.14.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 6.14.8 Host Interface Controller (HIC)
        1. 6.14.8.1 HIC Electrical Data and Timing
          1. 6.14.8.1.1 HIC Timing Requirements
          2. 6.14.8.1.2 HIC Switching Characteristics
          3. 6.14.8.1.3 HIC Timing Diagrams
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
      2. 7.3.2 Flash Memory Map
        1. 7.3.2.1 Addresses of Flash Sectors
      3. 7.3.3 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Fast Integer Division Unit
      3. 7.6.3 Trigonometric Math Unit (TMU)
      4. 7.6.4 VCRC Unit
    7. 7.7  Embedded Real-Time Analysis and Diagnostic (ERAD)
    8. 7.8  Background CRC-32 (BGCRC)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Dual Code Security Module
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Key Device Features
    2. 8.2 Application Information
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Servo Drive Control Module
          1. 8.2.1.1.1 System Block Diagram
          2. 8.2.1.1.2 Servo Drive Control Module Resources
        2. 8.2.1.2 Server or Telecom Power Supply Unit (PSU)
          1. 8.2.1.2.1 System Block Diagram
          2. 8.2.1.2.2 Server and Telecom PSU Resources
        3. 8.2.1.3 Merchant Telecom Rectifiers
          1. 8.2.1.3.1 System Block Diagram
          2. 8.2.1.3.2 Merchant Telecom Rectifiers Resources
        4. 8.2.1.4 EV Charging Station Power Module
          1. 8.2.1.4.1 System Block Diagram
          2. 8.2.1.4.2 EV Charging Station Power Module Resources
        5. 8.2.1.5 Air-conditioner Outdoor Unit
          1. 8.2.1.5.1 System Block Diagram
          2. 8.2.1.5.2 Air Conditioner Outdoor Unit Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device and Development Support Tool Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.2 Digital Signals

Table 5-3 Digital Signals
SIGNAL NAMEPIN TYPEDESCRIPTIONGPIO80 QFP64 QFP48 QFP
ADCSOCAOOADC Start of Conversion A for External ADC33, 838, 5832, 4725
ADCSOCBOOADC Start of Conversion B for External ADC10, 3249, 7640, 6332
CANA_RXICAN-A Receive12, 18, 3, 30, 33, 35, 51, 36, 38, 48, 50, 60, 7430, 32, 39, 41, 49, 6124, 25, 31, 33, 39, 47
CANA_TXOCAN-A Transmit13, 17, 19, 2, 31, 32, 37, 42, 35, 40, 46, 49, 51, 59, 6129, 34, 37, 40, 42, 48, 5023, 29, 32, 34, 38, 40
CLB_OUTPUTXBAR1OCLB Output X-BAR Output 119, 2251, 6742, 5634
CLB_OUTPUTXBAR2OCLB Output X-BAR Output 239, 756, 6846, 5743
CLB_OUTPUTXBAR3OCLB Output X-BAR Output 342, 4457, 69
CLB_OUTPUTXBAR4OCLB Output X-BAR Output 443, 4554, 73
CLB_OUTPUTXBAR5OCLB Output X-BAR Output 55, 858, 7447, 6147
CLB_OUTPUTXBAR6OCLB Output X-BAR Output 615, 459, 784838
CLB_OUTPUTXBAR7OCLB Output X-BAR Output 71, 1462, 795141
CLB_OUTPUTXBAR8OCLB Output X-BAR Output 8663, 8052, 6442, 48
EPWM1_AOePWM-1 Output A301, 635242
EPWM1_BOePWM-1 Output B1, 312, 625141
EPWM2_AOePWM-2 Output A2, 4161, 6650, 5540
EPWM2_BOePWM-2 Output B3, 4060, 6449, 5339
EPWM3_AOePWM-3 Output A14, 459, 794838
EPWM3_BOePWM-3 Output B15, 574, 786147
EPWM4_AOePWM-4 Output A22, 667, 8056, 6448
EPWM4_BOePWM-4 Output B23, 765, 6854, 5743
EPWM5_AOePWM-5 Output A16, 839, 5833, 4726
EPWM5_BOePWM-5 Output B17, 940, 7534, 62
EPWM6_AOePWM-6 Output A10, 1850, 7641, 6333
EPWM6_BOePWM-6 Output B11, 1937, 5131, 4234
EPWM7_AOePWM-7 Output A12, 2836, 42, 302, 24
EPWM7_BOePWM-7 Output B13, 293, 351, 291, 23
EQEP1_AIeQEP-1 Input A10, 25, 28, 35, 40, 44, 64, 42, 48, 64, 69, 76, 802, 39, 53, 63, 642, 31, 48
EQEP1_BIeQEP-1 Input B11, 29, 37, 41, 73, 37, 46, 66, 681, 31, 37, 55, 571, 29, 43
EQEP1_INDEXI/OeQEP-1 Index13, 17, 23, 31, 39, 43, 92, 35, 40, 54, 56, 65, 7529, 34, 46, 54, 6223
EQEP1_STROBEI/OeQEP-1 Strobe12, 16, 22, 30, 42, 81, 36, 39, 57, 58, 6730, 33, 47, 5624, 26
EQEP2_AIeQEP-2 Input A11, 14, 18, 2437, 41, 50, 7931, 35, 4127, 33
EQEP2_BIeQEP-2 Input B15, 16, 19, 25, 3338, 39, 42, 51, 7832, 33, 4225, 26, 34
EQEP2_INDEXI/OeQEP-2 Index26, 29, 393, 43, 561, 461
EQEP2_STROBEI/OeQEP-2 Strobe27, 28, 44, 44, 592, 482, 38
ERRORSTSOError Status Output. When used, this signal requires an external pulldown.24, 28, 293, 4, 411, 2, 351, 2, 27
FSIRXA_CLKIFSIRX-A Input Clock13, 30, 33, 39, 41, 35, 38, 56, 59, 6329, 32, 46, 48, 5223, 25, 38, 42
FSIRXA_D0IFSIRX-A Data Input 012, 3, 32, 4036, 49, 60, 6430, 40, 49, 5324, 32, 39
FSIRXA_D1IFSIRX-A Data Input 111, 2, 31, 412, 37, 61, 6631, 50, 5540
FSITXA_CLKOFSITX-A Output Clock10, 27, 44, 744, 68, 69, 7657, 6343
FSITXA_D0OFSITX-A Data Output 026, 45, 6, 943, 73, 75, 8062, 6448
FSITXA_D1OFSITX-A Data Output 125, 46, 5, 6, 842, 58, 6, 74, 8047, 61, 6447, 48
FSITXA_TDM_CLKIFSITX-A Time Division Multiplexed Clock Input18, 850, 5841, 4733
FSITXA_TDM_D0IFSITX-A Time Division Multiplexed Data Input10, 1951, 7642, 6334
FSITXA_TDM_D1IFSITX-A Time Division Multiplexed Additional Data Input1625141
GPIO0I/OGeneral-Purpose Input Output 0635242
GPIO1I/OGeneral-Purpose Input Output 11625141
GPIO2I/OGeneral-Purpose Input Output 22615040
GPIO3I/OGeneral-Purpose Input Output 33604939
GPIO4I/OGeneral-Purpose Input Output 44594838
GPIO5I/OGeneral-Purpose Input Output 55746147
GPIO6I/OGeneral-Purpose Input Output 66806448
GPIO7I/OGeneral-Purpose Input Output 77685743
GPIO8I/OGeneral-Purpose Input Output 885847
GPIO9I/OGeneral-Purpose Input Output 997562
GPIO10I/OGeneral-Purpose Input Output 10107663
GPIO11I/OGeneral-Purpose Input Output 11113731
GPIO12I/OGeneral-Purpose Input Output 1212363024
GPIO13I/OGeneral-Purpose Input Output 1313352923
GPIO14I/OGeneral-Purpose Input Output 141479
GPIO15I/OGeneral-Purpose Input Output 151578
GPIO16I/OGeneral-Purpose Input Output 1616393326
GPIO17I/OGeneral-Purpose Input Output 17174034
GPIO18_X2I/OGeneral-Purpose Input Output 18_X218504133
GPIO19_X1I/OGeneral-Purpose Input Output 19_X119514234
GPIO22I/OGeneral-Purpose Input Output 22226756
GPIO23I/OGeneral-Purpose Input Output 23236554
GPIO24I/OGeneral-Purpose Input Output 2424413527
GPIO25I/OGeneral-Purpose Input Output 252542
GPIO26I/OGeneral-Purpose Input Output 262643
GPIO27I/OGeneral-Purpose Input Output 272744
GPIO28I/OGeneral-Purpose Input Output 2828422
GPIO29I/OGeneral-Purpose Input Output 2929311
GPIO30I/OGeneral-Purpose Input Output 30301
GPIO31I/OGeneral-Purpose Input Output 31312
GPIO32I/OGeneral-Purpose Input Output 3232494032
GPIO33I/OGeneral-Purpose Input Output 3333383225
GPIO34I/OGeneral-Purpose Input Output 343477
GPIO35I/OGeneral-Purpose Input Output 3535483931
GPIO37I/OGeneral-Purpose Input Output 3737463729
GPIO39I/OGeneral-Purpose Input Output 39395646
GPIO40I/OGeneral-Purpose Input Output 40406453
GPIO41I/OGeneral-Purpose Input Output 41416655
GPIO42I/OGeneral-Purpose Input Output 424257
GPIO43I/OGeneral-Purpose Input Output 434354
GPIO44I/OGeneral-Purpose Input Output 444469
GPIO45I/OGeneral-Purpose Input Output 454573
GPIO46I/OGeneral-Purpose Input Output 46466
GPIO61I/OGeneral-Purpose Input Output 6161
GPIO62I/OGeneral-Purpose Input Output 6262
GPIO63I/OGeneral-Purpose Input Output 6363
HIC_A0IHIC Address 085847
HIC_A1IHIC Address 12, 2643, 615040
HIC_A2IHIC Address 21625141
HIC_A3IHIC Address 3236554
HIC_A4IHIC Address 427, 4144, 6655
HIC_A5IHIC Address 5226756
HIC_A6IHIC Address 642, 757, 685743
HIC_A7IHIC Address 743, 554, 746147
HIC_BASESEL0IHIC Base Address Range Select 025, 942, 7562
HIC_BASESEL1IHIC Base Address Range Select 1635242
HIC_BASESEL2IHIC Base Address Range Select 24594838
HIC_D0I/OHIC Data 026, 3338, 433225
HIC_D1I/OHIC Data 116, 2739, 443326
HIC_D2I/OHIC Data 217, 4240, 5734
HIC_D3I/OHIC Data 324, 4341, 543527
HIC_D4I/OHIC Data 43, 560, 7449, 6139, 47
HIC_D5I/OHIC Data 513, 40, 4435, 64, 6929, 5323
HIC_D6I/OHIC Data 611, 4537, 7331
HIC_D7I/OHIC Data 739, 4456, 6946
HIC_D8I/OHIC Data 830, 81, 5847
HIC_D9I/OHIC Data 92, 3461, 775040
HIC_D10I/OHIC Data 101, 312, 625141
HIC_D11I/OHIC Data 1113, 2335, 6529, 5423
HIC_D12I/OHIC Data 1215, 4166, 7855
HIC_D13I/OHIC Data 1312, 2236, 6730, 5624
HIC_D14I/OHIC Data 146, 768, 8057, 6443, 48
HIC_D15I/OHIC Data 1514, 574, 796147
HIC_INTOHIC Device Interrupt12, 18, 3236, 49, 5030, 40, 4124, 32, 33
HIC_NBE0IHIC Byte Enable 011, 1937, 5131, 4234
HIC_NBE1IHIC Byte Enable 134, 40, 664, 77, 8053, 6448
HIC_NCSIHIC Chip Select29311
HIC_NOEOHIC Output Enable28, 34, 602, 492, 39
HIC_NRDYOHIC Ready37, 946, 7537, 6229
HIC_NWEIHIC Data Write Enable10, 35, 4, 4648, 59, 6, 7639, 48, 6331, 38
I2CA_SCLI/ODI2C-A Open-Drain Bidirectional Clock1, 18, 27, 33, 37, 43, 838, 44, 46, 50, 54, 58, 6232, 37, 41, 47, 5125, 29, 33, 41
I2CA_SDAI/ODI2C-A Open-Drain Bidirectional Data10, 19, 26, 32, 35, 4243, 48, 49, 51, 57, 63, 7639, 40, 42, 52, 6331, 32, 34, 42
I2CB_SCLI/ODI2C-B Open-Drain Bidirectional Clock15, 29, 3, 93, 60, 75, 781, 49, 621, 39
I2CB_SDAI/ODI2C-B Open-Drain Bidirectional Data14, 2, 28, 344, 61, 77, 792, 502, 40
LINA_RXILIN-A Receive23, 29, 33, 35, 423, 38, 48, 57, 651, 32, 39, 541, 25, 31
LINA_TXOLIN-A Transmit22, 28, 32, 37, 464, 46, 49, 6, 672, 37, 40, 562, 29, 32
LINB_RXILIN-B Receive11, 13, 15, 19, 23, 41, 935, 37, 51, 65, 66, 75, 7829, 31, 42, 54, 55, 6223, 34
LINB_TXOLIN-B Transmit10, 12, 14, 18, 22, 24, 4036, 41, 50, 64, 67, 76, 7930, 35, 41, 53, 56, 6324, 27, 33
OUTPUTXBAR1OOutput X-BAR Output 12, 24, 3441, 61, 7735, 5027, 40
OUTPUTXBAR2OOutput X-BAR Output 225, 3, 3742, 46, 6037, 4929, 39
OUTPUTXBAR3OOutput X-BAR Output 314, 26, 4, 543, 59, 74, 7948, 6138, 47
OUTPUTXBAR4OOutput X-BAR Output 415, 27, 33, 638, 44, 78, 8032, 6425, 48
OUTPUTXBAR5OOutput X-BAR Output 528, 42, 74, 57, 682, 572, 43
OUTPUTXBAR6OOutput X-BAR Output 629, 43, 93, 54, 751, 621
OUTPUTXBAR7OOutput X-BAR Output 711, 16, 30, 441, 37, 39, 6931, 3326
OUTPUTXBAR8OOutput X-BAR Output 817, 31, 452, 40, 7334
PMBUSA_ALERTI/ODPMBus-A Open-Drain Bidirectional Alert13, 19, 27, 37, 4335, 44, 46, 51, 5429, 37, 4223, 29, 34
PMBUSA_CTLI/OPMBus-A Control Signal - Slave Input/Master Output12, 18, 26, 35, 4236, 43, 48, 50, 5730, 39, 4124, 31, 33
PMBUSA_SCLI/ODPMBus-A Open-Drain Bidirectional Clock15, 16, 24, 3, 35, 4139, 41, 48, 60, 66, 7833, 35, 39, 49, 5526, 27, 31, 39
PMBUSA_SDAI/ODPMBus-A Open-Drain Bidirectional Data14, 17, 2, 25, 34, 4040, 42, 61, 64, 77, 7934, 50, 5340
SCIA_RXISCI-A Receive Data17, 25, 28, 3, 35, 94, 40, 42, 48, 60, 752, 34, 39, 49, 622, 31, 39
SCIA_TXOSCI-A Transmit Data16, 2, 24, 29, 37, 83, 39, 41, 46, 58, 611, 33, 35, 37, 47, 501, 26, 27, 29, 40
SPIA_CLKI/OSPI-A Clock12, 18, 3, 936, 50, 60, 7530, 41, 49, 6224, 33, 39
SPIA_SIMOI/OSPI-A Slave In, Master Out (SIMO)11, 16, 2, 837, 39, 58, 6131, 33, 47, 5026, 40
SPIA_SOMII/OSPI-A Slave Out, Master In (SOMI)1, 10, 13, 1735, 40, 62, 7629, 34, 51, 6323, 41
SPIA_STEI/OSPI-A Slave Transmit Enable (STE)11, 19, 537, 51, 63, 7431, 42, 52, 6134, 42, 47
SPIB_CLKI/OSPI-B Clock14, 22, 26, 28, 32, 44, 43, 49, 59, 67, 792, 40, 48, 562, 32, 38
SPIB_SIMOI/OSPI-B Slave In, Master Out (SIMO)24, 30, 40, 71, 41, 64, 6835, 53, 5727, 43
SPIB_SOMII/OSPI-B Slave Out, Master In (SOMI)16, 25, 31, 41, 62, 39, 42, 66, 8033, 55, 6426, 48
SPIB_STEI/OSPI-B Slave Transmit Enable (STE)15, 23, 27, 29, 333, 38, 44, 65, 781, 32, 541, 25
SYNCOUTOExternal ePWM Synchronization Pulse39, 656, 8046, 6448
TDIIJTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input.35483931
TDOOJTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input.37463729
X1ICrystal oscillator input or single-ended clock input. The device initialization software must configure this pin before the crystal oscillator is enabled. To use this oscillator, a quartz crystal circuit must be connected to X1 and X2. This pin can also be used to feed a single-ended 3.3-V level clock. For more information about the ALT functionality, see the table that is in the External Oscillator (XTAL) section of the System Control chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.19514234
X2OCrystal oscillator output. For more information about the ALT functionality, see the table that is in the External Oscillator (XTAL) section of the System Control chapter in the TMS320F28002x Real-Time Microcontrollers Technical Reference Manual.18504133
XCLKOUTOExternal Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device.16, 1839, 5033, 4126, 33