SPRSP45B March 2020 – December 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
PRODUCTION DATA
Table 7-4 lists the minimum required Flash wait states with different clock sources and frequencies. Wait state is the value set in register FRDCNTL[RWAIT].
CPUCLK (MHz) | EXTERNAL OSCILLATOR OR CRYSTAL | INTOSC1 OR INTOSC2 | ||
---|---|---|---|---|
NORMAL OPERATION | BANK OR PUMP SLEEP(1) | NORMAL OPERATION | BANK OR PUMP SLEEP(1) | |
97 < CPUCLK ≤ 100 | 4 | 4 | 5 | |
80 < CPUCLK ≤ 97 | 4 | |||
77 < CPUCLK ≤ 80 | 3 | 3 | 4 | |
60 < CPUCLK ≤ 77 | 3 | |||
58 < CPUCLK ≤ 60 | 2 | 2 | 3 | |
40 < CPUCLK ≤ 58 | 2 | |||
38 < CPUCLK ≤ 40 | 1 | 1 | 2 | |
20 < CPUCLK ≤ 38 | 1 | |||
19 < CPUCLK ≤ 20 | 0 | 0 | 1 | |
CPUCLK ≤ 19 | 0 |
The F28002x devices have an improved 128-bit prefetch buffer that provides high flash code execution efficiency across wait states. Figure 7-15 and Figure 7-16 illustrate typical efficiency across wait-state settings compared to previous-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer will depend on how many branches are present in application software. Two examples of linear code and if-then-else code are provided.
Table 7-5 lists the Flash parameters.
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Program Time(1) | 128 data bits + 16 ECC bits | 150 | 300 | µs | |
8KB sector | 50 | 100 | ms | ||
EraseTime(2)(3) at < 25 cycles | 8KB sector | 15 | 100 | ms | |
EraseTime(2)(3) at 1000 cycles | 8KB sector | 25 | 350 | ms | |
EraseTime(2)(3) at 2000 cycles | 8KB sector | 30 | 600 | ms | |
EraseTime(2)(3) at 20K cycles | 8KB sector | 120 | 4000 | ms | |
Nwec Write/Erase Cycles per sector | 20000 | cycles | |||
Nwec Write/Erase Cycles for entire Flash (combined all sectors) | 100000 | cycles | |||
tretention Data retention duration at TJ = 85oC | 20 | years |
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit word may only be programmed once per write/erase cycle.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-bit word may only be programmed once. The exceptions are: