SLUSBX9I March   2014  – July 2019 TPS23861

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Detailed Pin Description
      2. 7.1.2 I2C Detailed Pin Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detection Resistance Measurement
      2. 7.3.2  Physical Layer Classification
      3. 7.3.3  Class and Detect Fields
      4. 7.3.4  Register State Following a Fault
      5. 7.3.5  Disconnect
      6. 7.3.6  Disconnect Threshold
      7. 7.3.7  Fast Shutdown Mode
      8. 7.3.8  Legacy Device Detection
      9. 7.3.9  VPWR Undervoltage and UVLO Events
      10. 7.3.10 Timer-Deferrable Interrupt Support
      11. 7.3.11 A/D Converter and I2C Interface
      12. 7.3.12 Independent Operation when the AUTO Bit is Set
      13. 7.3.13 I2C Slave Address and AUTO Bit Programming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off
      2. 7.4.2 Manual
      3. 7.4.3 Semi-Auto
      4. 7.4.4 Auto
      5. 7.4.5 Push-Button Power On Response
      6. 7.4.6 TSTART Indicators of Detect and Class Failures
      7. 7.4.7 Device Power On Initialization
    5. 7.5 Register Map – I2C-Addressable
      1. 7.5.1  Interrupt Register
      2. 7.5.2  Interrupt Enable Register
      3. 7.5.3  Power Event Register
      4. 7.5.4  Detection Event Register
      5. 7.5.5  Fault Event Register
      6. 7.5.6  Start/ILIM Event Register
      7. 7.5.7  Supply Event Register
      8. 7.5.8  Port n Status Register
        1. 7.5.8.1 Port 1 Status Register
        2. 7.5.8.2 Port 2 Status Register
        3. 7.5.8.3 Port 3 Status Register
        4. 7.5.8.4 Port 4 Status Register
      9. 7.5.9  Power Status Register
      10. 7.5.10 I2C Slave Address Register
      11. 7.5.11 Operating Mode Register
      12. 7.5.12 Disconnect Enable Register
      13. 7.5.13 Detect/Class Enable Register
      14. 7.5.14 Port Power Priority Register
      15. 7.5.15 Timing Configuration Register
      16. 7.5.16 General Mask 1 Register
      17. 7.5.17 Detect/Class Restart Register
      18. 7.5.18 Power Enable Register
      19. 7.5.19 Reset Register
      20. 7.5.20 Legacy Detect Mode Register
      21. 7.5.21 Two-Event Classification Register
      22. 7.5.22 Interrupt Timer Register
      23. 7.5.23 Disconnect Threshold Register
        1. 7.5.23.1 Bits Description
      24. 7.5.24 ICUTnm CONFIG Register
        1. 7.5.24.1 ICUT21 CONFIG Register
        2. 7.5.24.2 ICUT43 CONFIG Register
        3. 7.5.24.3 Bits Description
      25. 7.5.25 Temperature Register
      26. 7.5.26 Input Voltage Register
      27. 7.5.27 Port n Current Register
        1. 7.5.27.1 Port 1 Current Register
        2. 7.5.27.2 Port 2 Current Register
        3. 7.5.27.3 Port 3 Current Register
        4. 7.5.27.4 Port 4 Current Register
      28. 7.5.28 Port n Voltage Register
        1. 7.5.28.1 Port 1 Voltage Register
        2. 7.5.28.2 Port 2 Voltage Register
        3. 7.5.28.3 Port 3 Voltage Register
        4. 7.5.28.4 Port 4 Voltage Register
      29. 7.5.29 PoE Plus Register
      30. 7.5.30 Firmware Revision Register
      31. 7.5.31 I2C Watchdog Register
      32. 7.5.32 Device ID Register
      33. 7.5.33 Cool Down/Gate Drive Register
      34. 7.5.34 Port n Detect Resistance Register
        1. 7.5.34.1 Port 1 Detect Resistance Register
          1. 7.5.34.1.1 Port 2 Detect Resistance Register
          2. 7.5.34.1.2 Port 3 Detect Resistance Register
          3. 7.5.34.1.3 Port 4 Detect Resistance Register
      35. 7.5.35 Port n Detect Voltage Difference Register
        1. 7.5.35.1 Port 1 Detect Voltage Difference Register
        2. 7.5.35.2 Port 2 Detect Voltage Difference Register
        3. 7.5.35.3 Port 3 Detect Voltage Difference Register
        4. 7.5.35.4 Port 4 Detect Voltage Difference Register
      36. 7.5.36 Reserved Registers
  8. 8 Application and Implementation
    1. 8.1 Introduction to PoE
    2. 8.2 Application Information
      1. 8.2.1 Kelvin Current Sensing Resistor
      2. 8.2.2 Connections on Unused Ports
    3. 8.3 Typical Application
      1. 8.3.1 Two Port, Auto Mode Application with External Port Reset
        1. 8.3.1.1 Design Requirements
      2. 8.3.2 Four Port, Auto Mode Application
        1. 8.3.2.1 Design Requirements
      3. 8.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller
        1. 8.3.3.1 Design Requirements
      4. 8.3.4 Detailed Design Procedure
        1. 8.3.4.1 Power Pin Bypass Capacitors
        2. 8.3.4.2 Per Port Components
        3. 8.3.4.3 System Level Components (not shown in the schematic diagrams)
      5. 8.3.5 Application Curves
    4. 8.4 System Examples
      1. 8.4.1 Overcurrent and Overload Protection
      2. 8.4.2 Inrush Protection
      3. 8.4.3 ICUT Current Limit
      4. 8.4.4 Foldback Protection (ILIM)
      5. 8.4.5 Kelvin Current Sensing Resistor
  9. 9 Power Supply Recommendations
    1. 9.1 VDD
    2. 9.2 VPWR
    3. 9.3 VPWR-RESET Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Port Current Kelvin Sensing
    2. 10.2 Layout Example
      1. 10.2.1 Component Placement and Routing Guidelines
        1. 10.2.1.1 Power Pin Bypass Capacitors
        2. 10.2.1.2 Per-Port Components
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

–40 ≤ TJ ≤ +125°C, VVDD = 3.3 V, VVPWR = 48 V, VDGND = VAGND, DGND, KSENSA and KSENSB connected to AGND, and all outputs are unloaded, PoEPn = 0, Positive currents are into pins, RS = 0.255 Ω, to KSENSA (SEN1 or SEN2) or to KSENSB (SEN3 or SEN4), RSENS = 22 Ω, RDRAIN = 47 Ω, typical values are at 25°C. All voltages are with respect to AGND, operating registers loaded with default values (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY VPWR
IVPWR VPWR current consumption VVPWR = 57 V 3.5 7 mA
VUVLOPW_F VPWR UVLO falling threshold Internal oscillator stops operating 14.5 17.5 V
VPUV_F VPWR Undervoltage falling threshold VPUV for port de-assertion 25 26.5 28 V
VUVLOPW_R VPWR UVLO rising threshold 15.5 18.5 V
INPUT SUPPLY VDD
IVDD VDD current consumption 5 6 mA
VUVDD_F VDD UVLO falling threshold For port turn off 2 2.2 2.4 V
VUVDD_R VDD UVLO rising threshold 2.4 2.6 2.8 V
VUVDD_HYS Hysteresis VDD UVLO(1) 0.4 V
DETECTION
IDET Detection current First detection point,
VVPWR – VDRAINn = 0 V		 145 160 190 µA
2nd detection point,
VVPWR – VDRAINn = 0 V		 235 270 300 µA
High Current detection point,
VVPWR – VDRAINn = 0 V		 490 540 585 µA
ΔIDET 2nd – 1st detection currents At VVPWR – VDRAINn = 0 V 98 110 118 µA
Vdetect Open circuit detection voltage VVPWR – VDRAINn 17.5 19 22 V
RREJ_LOW Rejected resistance low range 0.85 15 kΩ
RREJ_HI Rejected resistance high range 33 50 kΩ
RACCEPT Accepted resistance range 19 25 26.5 kΩ
RSHORT Shorted port threshold 350 Ω
ROPEN Open port threshold 55 kΩ
CLASSIFICATION
VCLASS Classification voltage VVPWR – VDRAINn, VSENn ≥ 0 mV , Iport ≥ 180 µA, 15.5 18.5 20.5 V
ICLASS_Lim Classification current limit VVPWR – VDRAINn = 0 V 70 90 mA
ICLASS_TH Classification threshold current Class 0-1 5 8 mA
Class 1-2 13 16 mA
Class 2-3 21 25 mA
Class 3-4 31 35 mA
Class 4- overcurrent 45 51 mA
VMARK Mark voltage 4 mA ≥ Iport ≥ 180 µA, VVPWR – VDRAINn 7 10 V
IMARK_Lim Mark sinking current Limit VVPWR – VDRAINn = 0 V 10 70 90 mA
GATE
VGOH Gate drive voltage VGATEn , IGATE = –1 μA 10 12.5 V
IGO- Gate sinking current with power-on reset, shutdown detected or port turn off command VGATEn = 5 V 80 100 mA
IGO short– Gate sinking current with port short-circuit VGATEn = 5 V, VSENn ≥ VSHORT (or VSHORT2X if 2x mode) 80 100 150 mA
IGO+ Gate sourcing current VGATEn = 0 V, IGATE = 0 39 50 63 µA
IGATE = 1 18 25 34 µA
DRAIN INPUT
VPGT Power good threshold Measured at VDRAINn 1.0 2.13 3 V
VSHT Shorted FET threshold Measured at VDRAINn 4 6 8 V
RDRAIN Resistance from DRAINn to VPWR Any operating mode except during detection or while the port is ON, including in device reset state 80 100 190 kΩ
IDRAIN DRAINn pin bias current VDRAINn = 48 V, port OFF (not in detection) 1 µA
VVPWR - VDRAINn = 30 V, port ON 75 100 µA
A/D CONVERTER
TCONV Conversion time , A/D #1 to 4 All ranges, each port current 0.65 0.8 1 ms
ADCBW(1) ADC integration bandwidth (–3 dB)(1) 320 Hz
TINT_CUR Integration (averaging) time, current Each port, port ON current 80 100 125 ms
TINT_DET Integration (averaging) time, detection(1) MAINS bit = 0 20 ms
Powered port voltage conversion scale factor and accuracy At VVPWR – VDRAINn = 57 V, 0°C to 125°C 15175 15565 15955 Counts
At VVPWR – VDRAINn = 44 V, 0°C to 125°C 11713 12015 12316 Counts
At VVPWR – VDRAINn = 57 V, –40°C to 125°C 15020 15565 16110 Counts
At VVPWR – VDRAINn = 44 V, –40°C to 125°C 11594 12015 12436 Counts
Powered port current conversion scale factor and accuracy At port current = 770 mA 12300 12616 12932 Counts
At port current = 7.5 mA 90 123 156 Counts
Input voltage conversion scale factor and accuracy At VVPWR = 57 V 15175 15565 15955 Counts
At VVPWR = 44 V 11713 12015 12316 Counts
VOS Powered port voltage conversion offset At VVPWR – VDRAINn = 0.3 V 0 600 mV
δV/VPORT Voltage reading accuracy At 44 V to 57 V –40°C to 125°C –3.5% 3.5%
At 44 V to 57 V 0°C to 125°C –2.5% 2.5%
δI/Iport Current reading accuracy At 50 mA to 770 mA –2.5% 2.5%
PORT CURRENT SENSE
VCUT ICUT limit VDRAINn = 0 V, ICUT port n[2:0] = 000, default 90.60 95.37 100.14 mV
VDRAINn = 0 V, ICUT port n[2:0] = 001 26.65 28.05 29.45 mV
VDRAINn = 0 V, ICUT port n[2:0] = 010 49.42 52.02 54.62 mV
VDRAINn = 0 V, ICUT port n[2:0] = 110 156.27 164.5 172.72 mV
VDRAINn = 0 V, ICUT port n[2:0] = 111 222.87 234.6 246.33 mV
δICUT/ICUT ICUT tolerance –5% 5%
VINRUSH IInrush limit At port turn on,
VVPWR – VDRAINn = 1 V		 10 23 31 mV
VVPWR - VDRAINn = 10 V 20 33 46 mV
VVPWR - VDRAINn = 30 V 102 114.7 mV
VVPWR – VDRAINn = 55 V 102 114.7 mV
VLIM ILIM limit with PoEPn = 0 VDRAINn = 1 V 102 114.7 mV
VDRAINn = 13 V 102 114.7 mV
VDRAINn = 30 V 15 23 31 mV
VDRAINn = 48 V 15 23 31 mV
VLIM2X ILIM limit with PoEPn = 1 VDRAINn = 1 V 260 270.3 285 mV
VDRAINn = 10 V 127 140 153 mV
VDRAINn = 30 V 15 23 31 mV
VDRAINn = 48 V 15 23 31 mV
VSHORT ISHORT threshold with PoEPn = 0 Threshold for GATE to be less than 1 V,
2 μs after application of pulse		 140 183 mV
VSHORT2X ISHORT threshold with PoEPn = 1 357 408 mV
IBIAS Sense pin bias current Port ON or during class -2.25 0 µA
VI(min) Disconnect threshold DCTHn = 00, default 1.275 2.55 mV
DCTHn = 01 2.55 5.1 mV
DCTHn = 10 5.1 10.2 mV
DCTHn = 11 8.5 17 mV
DIGITAL INTERFACE AT VVDD = 3.3 V
VIH Digital input high 2.1 V
VIL Digital input low 0.9 V
VIT_HYS Input voltage hysteresis (SCL, SDAI, AIN, A3, RESET, SHTDWN) 0.17 V
VOL Digital output Low, SDAO IOL = 9 mA 0.4 V
Digital output Low, INT IOL = 3 mA 0.4 V
Rpullup Pullup resistor to VDD RESET, AIN, A3, SHTDWN 30 50 80 kΩ
AOUT OUTPUT
VOL_AOUT AOUT output low voltage During slave address programming, IAOUT = 1 mA 0.7 V
EEPROM (I2C Slave Address)
nEE_cyc EEPROM endurance 40 V < VVPWR < 57 V 25 cycles
tWC Write cycle time (byte or page) 40 V < VVPWR < 57 V 10 100 ms
THERMAL SHUTDOWN
TSD Thermal shutdown temperature Temperature rising 143 154 161 °C
Hysteresis(1) 8 °C
(1) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product warranty.