SLUSBX9I March 2014 – July 2019 TPS23861
Legacy PDs which are not compliant with IEEE 802.3at can be identified on port n under control of the LEGMOD field in the Legacy Detect Mode Register. Two modes of legacy detection are supported. When LEGMODn = 10, port n is probed for IEEE 802.3at-based compliance (based on resistance measurement) followed by a capacitance-based detection scheme for legacy devices. When LEGMODn= 01, port n performs a capacitance-based detection scheme only. This allows the host to probe for a potential legacy PD without pre-charging the PD capacitance before trying to measure the value of the capacitance.
To measure capacitance, a fixed charge is injected into the Power Interface (PI) and the voltage difference induced by the charge is measured and reported in the Port n Detect Voltage Difference Registers. The capacitance is inversely proportional to the voltage difference. The voltage difference is compared against thresholds to accept capacitance values above 6 µF pursuant to the qualifications which follow.
The Port n Detect Voltage Difference Register consists of two contiguous bytes in the I2C addressable register space. Together these registers contain a 12-bit unsigned representation of the voltage difference along with a 4-bit status field named VDSn. When VDSn = 0001 the voltage-difference value represents a valid measurement. The capacitance measurement may fail due to an excessively small or large capacitance, or an input capacitance which cannot be discharged because it is behind a diode. These cases are reported in the VDSn field as well as in the DETECT Pn field in the Port n Status Registers. See Table 5.
|Minimum measurable capacitance||Maximum 500-kΩ parallel resistance; maximum measurement voltage of 16.5 V at port||6.1||μF|
|Maximum measurable capacitance||Minimum 17-kΩ parallel resistance||100||μF|
|Maximum measurable capacitance||Minimum 10-kΩ parallel resistance||67||μF|
|Nominal port charging current||540||μA|
|Nominal measurement time||150||ms|
|Minimum voltage at port for commencement of measurement||0.4||V|
|Maximum voltage at port for commencement of measurement||2.4||V|
|Duration of port-discharge period||First discharge attempt||250||ms|
|Duration of port-discharge period||Second discharge attempt||500||ms|
|Maximum voltage at port at the beginning or end of measurement||16.5||V|
A resistance in parallel with the capacitance at the input of the PD affects the accuracy of the capacitance-measurement algorithm. A parallel resistance causes the capacitance on the port to appear higher. This fact is reflected in Table 5 . Capacitance up to 100 μF can be measured with a parallel resistance as low as 17 kΩ, whereas if the parallel resistance is as low as 10-kΩ, capacitance up to 67 μF can be measured.
The voltage on the port must be in the range of 0.4 V to 2.4 V to begin capacitance measurement. This voltage as measured at the PSE includes the voltage drops across any diodes in the path of the capacitance. If the voltage measured is too high (due to charge on the PD capacitance), the TPS23861 makes two attempts to discharge the port by applying a 100-kΩ load across the port. The first discharge attempt is 250-ms duration; the second attempt 500 ms.
It may not be possible to discharge the PD capacitance rapidly if the capacitance is on the other side of a diode.
If the capacitance-measurement algorithm is unable to discharge the port to less than 2.4 V after two attempts, the algorithm terminates the attempt to measure port capacitance, and report an Unable to achieve 2.4 V to take first measurement status in the VDSn field of the Port n Detect Voltage Difference Registers. A status of Capacitance measurement invalid: Insufficient Δv measured is reported in the Port n Status Registers. A status of Unable to discharge PD input capacitance to 2.4 V before timeout, is reported in the VDSn field of the Port n Detect Voltage Difference Registers. The host has the option of imposing a longer discharge time and retrying.
Erratic results may be obtained when performing legacy detect in Semi-Auto Mode due to the repeated charging of the load. If the capacitive load is behind a diode or is in parallel with a high resistance, the capacitor may eventually charge beyond 2.4 V, and the capacitance measurement fails. Manual Mode is recommended for legacy detect when there is no information about the load, or if the load input capacitance charges beyond 2.4 V in Semi-Auto Mode.
If the port is open or a small capacitance is present on the port, the port voltage rises quickly when the capacitance-measuring current is applied. The voltage on the port is limited to approximately 18 V by an internal clamp. A status of Capacitance measurement invalid: Detect measurement beyond clamp voltage is reported in the DETECT Pn field of the Port n Status Registers. Depending on the size of the small capacitance, a status of First measurement exceeds VDet-clamp (min) or Second measurement exceeds VDet-clamp (min) is reported in the VDSn field of the PORT n Detect Voltage Difference Registers.
If a large capacitance or short circuit is present on the port, the port voltage will not change sufficiently over the port charging time to assure a reliable measurement. In this case, a status of Capacitance measurement invalid: Insufficient Δv measured is reported in the Port n Status Registers, and a status of Δv < 0.5 V (insufficient signal) or Unable to achieve 0.4V to take first measurement before timeout is reported in the VDSn field of the Port n Detect Voltage Difference Registers.
Legacy detect is an exceptional condition which warrants special handling by the host system. Consequently, legacy-detect operation will not be fully supported in Auto Mode. If a legacy device is detected during detection in any mode of operation, the detect status is reported as Legacy Detect in the Port n Status Register Detect Pn field. It is up to the host to power on the port. If a port is in Auto Mode, legacy detection is enabled and a legacy device is detected, the detect status is reported as Legacy Detect in the Port n Status Registers Detect Pn field, but the port will not power on automatically. In this respect, operation of the port is identical to the Semi-Auto Mode.
In general, it is expected that a legacy device will not respond to a request for classification. Therefore, if the portis in Semi-Auto, Auto Mode or Manual Mode and LEGMOD = 01, the PSE will not automatically initiate a classification cycle even if the CLEn bit is set. On the other hand, if LEGMOD = 10, the TPS23861 is operating in Semi-Auto or Auto Mode, classification is enabled via the CLEn bit, and a Resistance valid detect status is returned in response to a standard resistance detection cycle, the TPS23861 follows the standard resistance detection cycle with a classification cycle. Furthermore, following classification, if in Auto Mode, if the classification status is not unknown, class mismatch or overcurrent, the port automatically powers up. Additionally if LEGMOD = 10, it is possible to initiate a classification cycle under manual control using the CLEn bit in the Detect/Class Enable Register or the RCLn bit in the Detect/Class Restart Register or power on the port under manual control using the PWONn bit in the Power Enable Register.
If LEGMODn = 10, and a Resistance valid detect status is returned in response to a standard resistance detection cycle the TPS23861 will not attempt to measure capacitance on the PI.