SLUSBX9I March 2014 – July 2019 TPS23861
Command = 27h with 1 Data Byte, Read/Write
|RESET OR POR VALUE||0||0||0||0||0||0||0||0|
TMR[3:0]: Non-critical interrupts may be deferred using an internal timer. Once loaded with a non-zero value, the internal timer counts continuously with period calculated as follows:
Non-critical interrupts generated within the TPS23861 will be passed to the interrupt-handling hardware whenever the timer counts down to 0. (The timer then reloads and continues to count.)
‘interrupt-handling hardware’ includes all interrupt-enabling functionality as well.
Critical and non-critical interrupts are defined in Table 6. When the TMR[3:0] field is read, the contents will be the contents last written by firmware.
When TMR[3:0] = 0 all interrupts will be handled as they are generated. In other words, this function is disabled when TMR[3:0] = 0000.
Reserved: Bits R27[7:4] are reserved for future use. Undesirable behavior may result if the value of these bits are changed from the reset value.