SLUSBX9I March   2014  – July 2019 TPS23861

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Detailed Pin Description
      2. 7.1.2 I2C Detailed Pin Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detection Resistance Measurement
      2. 7.3.2  Physical Layer Classification
      3. 7.3.3  Class and Detect Fields
      4. 7.3.4  Register State Following a Fault
      5. 7.3.5  Disconnect
      6. 7.3.6  Disconnect Threshold
      7. 7.3.7  Fast Shutdown Mode
      8. 7.3.8  Legacy Device Detection
      9. 7.3.9  VPWR Undervoltage and UVLO Events
      10. 7.3.10 Timer-Deferrable Interrupt Support
      11. 7.3.11 A/D Converter and I2C Interface
      12. 7.3.12 Independent Operation when the AUTO Bit is Set
      13. 7.3.13 I2C Slave Address and AUTO Bit Programming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off
      2. 7.4.2 Manual
      3. 7.4.3 Semi-Auto
      4. 7.4.4 Auto
      5. 7.4.5 Push-Button Power On Response
      6. 7.4.6 TSTART Indicators of Detect and Class Failures
      7. 7.4.7 Device Power On Initialization
    5. 7.5 Register Map – I2C-Addressable
      1. 7.5.1  Interrupt Register
      2. 7.5.2  Interrupt Enable Register
      3. 7.5.3  Power Event Register
      4. 7.5.4  Detection Event Register
      5. 7.5.5  Fault Event Register
      6. 7.5.6  Start/ILIM Event Register
      7. 7.5.7  Supply Event Register
      8. 7.5.8  Port n Status Register
        1. 7.5.8.1 Port 1 Status Register
        2. 7.5.8.2 Port 2 Status Register
        3. 7.5.8.3 Port 3 Status Register
        4. 7.5.8.4 Port 4 Status Register
      9. 7.5.9  Power Status Register
      10. 7.5.10 I2C Slave Address Register
      11. 7.5.11 Operating Mode Register
      12. 7.5.12 Disconnect Enable Register
      13. 7.5.13 Detect/Class Enable Register
      14. 7.5.14 Port Power Priority Register
      15. 7.5.15 Timing Configuration Register
      16. 7.5.16 General Mask 1 Register
      17. 7.5.17 Detect/Class Restart Register
      18. 7.5.18 Power Enable Register
      19. 7.5.19 Reset Register
      20. 7.5.20 Legacy Detect Mode Register
      21. 7.5.21 Two-Event Classification Register
      22. 7.5.22 Interrupt Timer Register
      23. 7.5.23 Disconnect Threshold Register
        1. 7.5.23.1 Bits Description
      24. 7.5.24 ICUTnm CONFIG Register
        1. 7.5.24.1 ICUT21 CONFIG Register
        2. 7.5.24.2 ICUT43 CONFIG Register
        3. 7.5.24.3 Bits Description
      25. 7.5.25 Temperature Register
      26. 7.5.26 Input Voltage Register
      27. 7.5.27 Port n Current Register
        1. 7.5.27.1 Port 1 Current Register
        2. 7.5.27.2 Port 2 Current Register
        3. 7.5.27.3 Port 3 Current Register
        4. 7.5.27.4 Port 4 Current Register
      28. 7.5.28 Port n Voltage Register
        1. 7.5.28.1 Port 1 Voltage Register
        2. 7.5.28.2 Port 2 Voltage Register
        3. 7.5.28.3 Port 3 Voltage Register
        4. 7.5.28.4 Port 4 Voltage Register
      29. 7.5.29 PoE Plus Register
      30. 7.5.30 Firmware Revision Register
      31. 7.5.31 I2C Watchdog Register
      32. 7.5.32 Device ID Register
      33. 7.5.33 Cool Down/Gate Drive Register
      34. 7.5.34 Port n Detect Resistance Register
        1. 7.5.34.1 Port 1 Detect Resistance Register
          1. 7.5.34.1.1 Port 2 Detect Resistance Register
          2. 7.5.34.1.2 Port 3 Detect Resistance Register
          3. 7.5.34.1.3 Port 4 Detect Resistance Register
      35. 7.5.35 Port n Detect Voltage Difference Register
        1. 7.5.35.1 Port 1 Detect Voltage Difference Register
        2. 7.5.35.2 Port 2 Detect Voltage Difference Register
        3. 7.5.35.3 Port 3 Detect Voltage Difference Register
        4. 7.5.35.4 Port 4 Detect Voltage Difference Register
      36. 7.5.36 Reserved Registers
  8. 8 Application and Implementation
    1. 8.1 Introduction to PoE
    2. 8.2 Application Information
      1. 8.2.1 Kelvin Current Sensing Resistor
      2. 8.2.2 Connections on Unused Ports
    3. 8.3 Typical Application
      1. 8.3.1 Two Port, Auto Mode Application with External Port Reset
        1. 8.3.1.1 Design Requirements
      2. 8.3.2 Four Port, Auto Mode Application
        1. 8.3.2.1 Design Requirements
      3. 8.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller
        1. 8.3.3.1 Design Requirements
      4. 8.3.4 Detailed Design Procedure
        1. 8.3.4.1 Power Pin Bypass Capacitors
        2. 8.3.4.2 Per Port Components
        3. 8.3.4.3 System Level Components (not shown in the schematic diagrams)
      5. 8.3.5 Application Curves
    4. 8.4 System Examples
      1. 8.4.1 Overcurrent and Overload Protection
      2. 8.4.2 Inrush Protection
      3. 8.4.3 ICUT Current Limit
      4. 8.4.4 Foldback Protection (ILIM)
      5. 8.4.5 Kelvin Current Sensing Resistor
  9. 9 Power Supply Recommendations
    1. 9.1 VDD
    2. 9.2 VPWR
    3. 9.3 VPWR-RESET Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Port Current Kelvin Sensing
    2. 10.2 Layout Example
      1. 10.2.1 Component Placement and Routing Guidelines
        1. 10.2.1.1 Power Pin Bypass Capacitors
        2. 10.2.1.2 Per-Port Components
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Register Map – I2C-Addressable

Table 10. I2C-Addressable Register Set Summary (1)(2)

CMD CODE REGISTER OR COMMAND NAME I2C R/W DATA BYTE RST STATE FIELD DESCRIPTION
00 Interrupt RO 1 1000,0000 SUPF STRTF IFAULT CLASC DETC DISF PGC PEC
01 Interrupt Enable R/W 1 1AA0,0A00 SUPEN STRTEN IFEN CLCEN DEEN DISEN PGSEN PESEN
02 Power Event RO 1 0000,0000 Power Good status change Power Enable status change
03 CoR 1 PGC4 PGC3 PGC2 PGC1 PEC4 PEC3 PEC2 PEC1
04 Detection Event RO 1 0000,0000 Classification Detection
05 CoR 1 CLSC4 CLSC3 CLSC2 CLSC1 DETC4 DETC3 DETC2 DETC1
06 Fault Event RO 1 0000,0000 Disconnect occurred ICUT fault occurred
07 CoR 1 DISF4 DISF3 DISF2 DISF1 ICUT4 ICUT3 ICUT2 ICUT1
08 Start/ILIM Event RO 1 0000,0000 ILIM fault occurred Start fault occurred
09 CoR 1 ILIM4 ILIM3 ILIM2 ILIM1 STRT4 STRT3 STRT2 STRT1
0A Supply Event RO 1 0011,0000 TSD - VDUV VPUV - - - -
0B CoR 1
0C Port 1 Status RO 1 0000,0000 CLASS P1 DETECT P1
0D Port 2 Status RO 1 0000,0000 CLASS P2 DETECT P2
0E Port 3 Status RO 1 0000,0000 CLASS P3 DETECT P3
0F Port 4 Status RO 1 0000,0000 CLASS P4 DETECT P4
10 Power Status RO 1 0000,0000 PG4 PG3 PG2 PG1 PE4 PE3 PE2 PE1
11 I2C Slave Address RO(3) 1 1010,0000 AUTO SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0
12 Operating Mode R/W 1 AAAA,AAAA Port 4 Mode Port 3 Mode Port 2 Mode Port 1 Mode
13 Disconnect Enable R/W 1 0000,AAAA - - - - DCDE4 DCDE3 DCDE2 DCDE1
14 Detect/Class ENABLE R/W 1 AAAA,AAAA CLE4 CLE3 CLE2 CLE1 DETE4 DETE3 DETE2 DETE1
15 Port PWR Priority R/W 1 AAAA,0000 FSE4 FSE3 FSE2 FSE1 - - - -
16 Timing Configuration R/W 1 0000,0000 TLIM TSTART TICUT TDIS
17 General Mask R/W 1 1000,0000 INTEN - - MAINS - - R M250
18 Detect/Class Restart WO 1 - RCL4 RCL3 RCL2 RCL1 RDET4 RDET3 RDET2 RDET1
19 Power Enable WO 1 - POFF4 POFF3 POFF2 POFF1 PWON4 PWON3 PWON2 POWN1
1A Reset WO 1 - CLRAIN CLINP - RESAL RESP4 RESP3 RESP2 RESP1
20 Legacy Detect Mode R/W 1 0000,0000 LEGMOD4 LEGMOD3 LEGMOD2 LEGMOD1
21 Two-Event Classification R/W 1 0A0A,0A0A TECLEN4 TECLEN3 TECLEN2 TECLEN1
27 Interrupt Timer R/W 1 0000,0000 R R R R TMR 3-0
29 Disconnect Threshold R/W 1 0000,0000 DCTH4 DCTH3 DCTH2 DCTH1
2A ICUT21 CONFIG R/W 1 0000,0000 - ICUT Port 2 - ICUT Port 1
2B ICUT43 CONFIG R/W 1 0000,0000 - ICUT Port 4 - ICUT Port 3
2C Temperature RO 0000,0000 Temperature (bits 7 to 0)
2E Input Voltage RO 2 0000,0000 Input voltage: LSByte
2F RO 0000,0000 - - Input voltage: MSByte (bits 13 to 8)
30 Port 1 Current RO 2 0000,0000 Port 1 current: LSByte
31 RO 0000,0000 - - Port 1 current: MSByte (bits 13 to 8)
32 Port 1 Voltage RO 2 0000,0000 Port 1 voltage: LSByte
33 RO 0000,0000 - - Port 1 voltage: MSByte (bits 13 to 8)
34 Port 2 Current RO 2 0000,0000 Port 2 current: LSByte
35 RO 0000,0000 - - Port 2 current: MSByte (bits 13 to 8)
36 Port 2 Voltage RO 2 0000,0000 Port 2 voltage: LSByte
37 RO 0000,0000 - - Port 2 voltage: MSByte (bits 13 to 8)
38 Port 3 Current RO 2 0000,0000 Port 3 current: LSByte
39 RO 0000,0000 - - Port 3 current: MSByte (bits 13 to 8)
3A Port 3 Voltage RO 2 0000,0000 Port 3 voltage: LSByte
3B RO 0000,0000 - - Port 3 voltage: MSByte (bits 13 to 8)
3C Port 4 Current RO 2 0000,0000 Port 4 current: LSByte
3D RO 0000,0000 - - Port 4 current: MSByte (bits 13 to 8)
3E Port 4 Voltage RO 2 0000,0000 Port 4 voltage: LSByte
3F RO 0000,0000 - - Port 4 voltage: MSByte (bits 13 to 8)
40 PoE Plus R/W 1 0000,---- POEP4 POEP3 POEP2 POEP1 - - - -
41 Firmware Revision RO 1 RRRR,RRRR Firmware revision
42 I2C Watchdog R/W 1 0001,0110 - - - Watchdog disable WDS
43 Device ID R/W 1 111,sr[4:0] Device ID number Silicon revision number
45 Cool Down/Gate Drive R/W 1 0000,0000 CLDN IGATE - - - - -
60 Port 1 Detect Resistance RO 2 0000,0000 Port 1 resistance: LSByte
61 RO 0000,0000 RS1 Port 1 resistance: MSByte (bits 13 to 8)
62 Port 2 Detect Resistance RO 2 0000,0000 Port 2 resistance: LSByte
63 RO 0000,0000 RS2 Port 2 resistance: MSByte (bits 13 to 8)
64 Port 3 Detect Resistance RO 2 0000,0000 Port 3 resistance: LSByte
65 RO 0000,0000 RS3 Port 3 resistance: MSByte (bits 13 to 8)
66 Port 4 Detect Resistance RO 2 0000,0000 Port 4 resistance: LSByte
67 RO 0000,0000 RS4 Port 4 resistance: MSByte (bits 13 to 8)
68 Port 1 Detect Voltage Difference RO 2 0000,0000 Port 1 voltage difference (bits 7 to 0)
69 RO 0000,0000 VDS1 Port 1 voltage difference: MSByte (bits 11 to 8)
6A Port 2 Detect Voltage Difference RO 2 0000,0000 Port 2 voltage difference (bits 7 to 0)
6B RO 0000,0000 VDS2 Port 2 voltage difference: MSByte (bits 11 to 8)
6C Port 3 Detect Voltage Difference RO 2 0000,0000 Port 3 voltage difference (bits 7 to 0)
6D RO 0000,0000 VDS3 Port 3 voltage difference: MSByte (bits 11 to 8)
6E Port 4 Detect Voltage Difference RO 2 0000,0000 Port 4 voltage difference (bits 7 to 0)
6F RO 0000,0000 VDS4 Port 4 voltage difference: MSByte (bits 11 to 8)
(1) Bits labeled "R" are reserved. Undesirable behavior may result if the value of these bits are changed from the reset value.
(2) Bits labeled “A” assume the state of the bit programmed into register 0x11 after POR.
(3) This register is Read/Write during slave address programming when preceded by the unlock code.