The device uses D-CAP4 control to achieve a fast load transient response while maintaining ease-of-use. The D-CAP4 control architecture includes an internal ripple generation network enabling the use of very low-ESR output capacitors such as multi-layered ceramic capacitors (MLCC) and low ESR polymer capacitors. No external current sensing network or voltage compensators are required with D-CAP4 control architecture. The role of the internal ripple generation network is to emulate the ripple component of the inductor current information and then combine with the voltage feedback signal to regulate the loop operation.

D-CAP4 control architecture reduces loop gain variation across V_OUT, enabling a fast load transient response across the entire output voltage range with one ramp setting. The R-C time-constant of the internal ramp circuit sets the zero frequency of the ramp, similar to other R-C based internal ramp generation architectures. The reduced variation in loop gain also mitigates the need for a feedforward capacitor to optimize the transient response. The ramp amplitude varies with V_IN to minimize variation in loop gain across input voltage, commonly referred to as input voltage feedforward. Lastly, the device uses internal circuitry to correct for the dc offset caused by the injected ramp, and significantly reduces the dc offset caused by the output ripple voltage, especially with light load current.

For any control topologies supporting no external compensation, there is a minimum range, maximum range, or both, for the output filter the control topologies can support. The output filter used for a typical buck converter is a low-pass L-C circuit. This L-C filter has double pole that Equation 1 describes.

Equation 1.

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency L-C double pole has a 180-degree drop in phase. At the output filter frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per decade and increases the phase by 90 degrees per decade above the zero frequency.

The inductor and capacitor selected for the output filter must be such that the f_P double pole of Equation 1 is located no higher than the value given in Table 6-1, then adjusted based on the nominal duty cycle in the application using Equation 2. Equation 2 scales up the f_P(TABLE) because, as the duty cycle increases the gain of the D-CAP4 ramp decreases, so the maximum L-C double pole also increases.

An L-C double pole frequency that violates these guidelines for each setting can be possible, but must be validated in the application with measurements.

After identifying the application requirements, the output inductance is typically designed so the inductor peak-to-peak ripple current is approximately between 15% and 40% of the maximum output current in the application. Choosing very small output capacitance leads to a high frequency L-C double pole which causes the overall loop gain to stay high until the L-C double pole frequency. Given the zero from the internal ripple generation network is a relatively high frequency as well, the loop with very small output capacitance can have too high of a crossover frequency which can cause instability. In general, where reasonable (or smaller) output capacitance is desired, output ripple requirement and load transient requirement can be used to determine the necessary output capacitance for stable operation.

If MLCCs are used, consider the derating characteristics to determine the final output capacitance for the design. For example, when using an MLCC with specifications of 10µF, X5R and 6.3V, the derating by DC bias and AC bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case is 40% and 4µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in the application.

As a simplified rule, if an output capacitor with an ESR zero that is less than 10 × the L-C double pole frequency, TI recommends to ignore when calculating the L-C double pole frequency for stability purposes. The L-C double pole frequency must be recalculated using only the low ESR MLCCs. For more accurate analysis when using mixed type output capacitors, TI recommends simulations or measurements.

For the maximum output capacitance recommendation, select the inductor and capacitor values so that the L-C double pole frequency is no less than 1/100th of the operating frequency. With this starting point, verify the small signal response on the board using the following criteria: The phase margin at the loop crossover is greater than 45 degrees. The actual maximum output capacitance can go higher as long as phase margin is greater than 45 degrees. However, a small signal measurement (Bode plot) must be done to confirm the design.

For large output filters with an L-C double pole near 1/100th of the operating frequency, additional phase boost can be required. A feedforward capacitor placed in parallel with R_{FB_HS} can boost the phase. See also the Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor application note.

Besides boosting the phase, a feedforward capacitor feeds more V_OUT node information into the FB node through AC coupling. This feedforward during load transient event enables faster response of the control loop to a V_OUT deviation. However, this feedforward during steady state operation also feeds more V_OUT ripple and noise into FB. High ripple and noise on FB usually leads to more jitter, or even double-pulse behavior. To determine the final feedforward capacitor value impacts to phase margin, consider load transient performance, ripple, and noise on FB. TI recommends using frequency analysis equipment to measure the crossover frequency and the phase margin.