SLVSHN0A September   2024  – October 2025 TPS548B23

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP4 Control
      2. 6.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 6.3.2.1 Powering the Device From a Single Bus
        2. 6.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 6.3.3  Multifunction Configuration (CFG1-5) Pins
        1. 6.3.3.1 Multifunction Configuration (CFG1-2) Pins (Internal Feedback)
        2. 6.3.3.2 Multifunction Configuration (CFG1-2) Pins (External Feedback)
        3. 6.3.3.3 Multifunction Configuration (CFG3-5) Pins
      4. 6.3.4  Enable
      5. 6.3.5  Soft Start
      6. 6.3.6  Power Good
      7. 6.3.7  Overvoltage and Undervoltage Protection
      8. 6.3.8  Output Voltage Setting (External Feedback Configuration)
      9. 6.3.9  Remote Sense
      10. 6.3.10 Low-side MOSFET Zero-Crossing
      11. 6.3.11 Current Sense and Positive Overcurrent Protection
      12. 6.3.12 Low-side MOSFET Negative Current Limit
      13. 6.3.13 Output Voltage Discharge
      14. 6.3.14 UVLO Protection
      15. 6.3.15 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Setting Point
        2. 7.2.2.2 Choose the Switching Frequency
        3. 7.2.2.3 Choose the Inductor
        4. 7.2.2.4 Choose the Output Capacitor
        5. 7.2.2.5 Choose the Input Capacitors (CIN)
        6. 7.2.2.6 VCC Bypass Capacitor
        7. 7.2.2.7 BOOT Capacitor
        8. 7.2.2.8 PG Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.5 Choose the Input Capacitors (CIN)

The device requires input bypass capacitors between both pairs of VIN and PGND pins to bypass the power-stage. The bypass capacitors must be placed as close as possible to the pins of the IC as the layout allows. At least 20µF nominal of ceramic capacitance and two high frequency ceramic bypass capacitors are required. A 0.1μF to 1μF capacitor must be placed as close as possible to both VIN pins 4 and 12 on the same side of the board of the device to provide the required high frequency bypass, to reduce the high frequency overshoot and undershoot on across the power-stage on the VIN and SW pins. TI recommends at least 1μF of bypass capacitance as close as possible to each VIN pin to minimize the input voltage ripple. The ceramic capacitors must be a high-quality dielectric of X6S or better for the high capacitance-to-volume ratio and stable characteristics across temperature. In addition to this requirement, more bulk capacitance can be needed on the input depending on the application to minimize variations on the input voltage during transient conditions.

Use Equation 25 to calculate the input capacitance required to meet a specific input ripple target. A recommended target input voltage ripple is 5% the minimum input voltage, 780mV in this example. The calculated input capacitance is 5.5μF. This example meets these two requirements with 2 × 10µF ceramic capacitors.

Equation 25. C I N > V O U T × I O U T × 1 - V O U T V I N m i n f S W × V I N m i n × V I N _ R I P P L E = 3.3 V × 20 A × 1 - 3.3 V 8 V 800   k H z × 8 V × 780 m V = 7.8 μ F

The capacitor must also have an RMS current rating greater than the maximum input RMS current in the application. Use Equation 27 to calculate the input RMS current the input capacitors must support. The result is9.9A in this example. The ceramic input capacitors have a current rating greater than this value.

Equation 26. I C I N ( R M S ) = V O U T V I N m i n × V I N m i n - V O U T V I N m i n × I O U T 2 + I R I P P L E 2 12
Equation 27. I C I N ( R M S ) = 3.3 V 8 V × 8 V - 3.3 V 8 V × 20 2 + 5.95 2 12 = 9.9 A

For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current, TI recommends the selection process in How to select input capacitors for a buck converter analog design journal.