SLVSHN0A September   2024  – October 2025 TPS548B23

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP4 Control
      2. 6.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 6.3.2.1 Powering the Device From a Single Bus
        2. 6.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 6.3.3  Multifunction Configuration (CFG1-5) Pins
        1. 6.3.3.1 Multifunction Configuration (CFG1-2) Pins (Internal Feedback)
        2. 6.3.3.2 Multifunction Configuration (CFG1-2) Pins (External Feedback)
        3. 6.3.3.3 Multifunction Configuration (CFG3-5) Pins
      4. 6.3.4  Enable
      5. 6.3.5  Soft Start
      6. 6.3.6  Power Good
      7. 6.3.7  Overvoltage and Undervoltage Protection
      8. 6.3.8  Output Voltage Setting (External Feedback Configuration)
      9. 6.3.9  Remote Sense
      10. 6.3.10 Low-side MOSFET Zero-Crossing
      11. 6.3.11 Current Sense and Positive Overcurrent Protection
      12. 6.3.12 Low-side MOSFET Negative Current Limit
      13. 6.3.13 Output Voltage Discharge
      14. 6.3.14 UVLO Protection
      15. 6.3.15 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Setting Point
        2. 7.2.2.2 Choose the Switching Frequency
        3. 7.2.2.3 Choose the Inductor
        4. 7.2.2.4 Choose the Output Capacitor
        5. 7.2.2.5 Choose the Input Capacitors (CIN)
        6. 7.2.2.6 VCC Bypass Capacitor
        7. 7.2.2.7 BOOT Capacitor
        8. 7.2.2.8 PG Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to +150°C, VVCC = 3.3V (external), VVIN = 4V to 16V. Typical values are at TJ = 25°C and VVIN = 12V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN) VIN quiescent current Non-switching, VEN = 2V, VFB = VFB_REG + 50mV, no external bias on VCC pin 970 µA
IQ(VIN) VIN quiescent current with external VCC bias TJ = 25°C, VIN = 12V, VEN = 2V, VFB = VFB_REG + 10mV (non-switching), 3.3V external bias on VCC pin 230 290 µA
ISD(VIN) VIN shutdown supply current VIN = 12 V, VEN = 0 V, no external bias on VCC pin 9.5 20 µA
IQ(VCC) VCC quiescent current TJ = 25°C, VIN = 12V, VEN = 2V, VFB = VFB_REG + 10mV (non-switching), 3.3 V external bias on VCC pin 860 µA
ISD(VCC) VCC shutdown current VEN = 0V, VIN = 0V, 3.3V external bias on VCC pin 90 µA
IVCC VCC external bias current (1) TJ = 25°C, VIN = 12V, VEN = 2V, regular switching, fSW = 600kHz, 3.3V external bias on VCC pin 10 mA
IVCC VCC external bias current (1) TJ = 25°C, VIN = 12V, VEN = 2V, regular switching,  fSW = 1200kHz,  3.3V external bias on VCC pin 16 mA
INTERNAL LDO (VCC)
VVCC Internal LDO output voltage 2.85 3.0 3.1 V
IVCC Internal LDO short-circuit current limit VVIN = 12V 210 mA
VCCUVLO(R) VCC UVLO rising threshold VVIN = 4V 2.73 2.85 V
VCCUVLO(F) VCC UVLO falling threshold VVIN = 4V 2.58 V
VCCUVLO(H) VCC UVLO hysteresis VVIN = 4V 0.15 V
FB threshold to turn off VCC LDO VFB falling, EN = 0V
 50 85 mV
UVLO
VINUVLO(R) VIN UVLO rising threshold VIN rising 3.88 3.95 V
VINUVLO(F) VIN UVLO falling threshold VIN falling 3.71 3.78 V
VINUVLO(H) VIN UVLO hysteresis 0.17 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.15 1.2 1.25 V
VEN(F) EN voltage falling threshold EN falling, disable switching 1.06 1.12 1.18 V
VEN(H) EN voltage hysteresis 80 mV
IEN(Hys) EN pin hysteresis current EN > VEN(R) 2.0 5 7.5 µA
EN internal pulldown resistance EN pin to AGND 0.74 1 1.27 MΩ
VENSTB(R) EN standby rising threshold EN rising, enable internal LDO, no switching 0.7 V
VENSTB(F) EN standby falling threshold EN Falling, disable internal LDO 0.3 0.6 V
PINSTRAP
CFGx_high CFGx logic high voltage level VCC = 5.0V 4.2 4.4 V
VCC = 3.3V 2.4 2.85 V
CFGx_low CFGx logic low voltage level VCC = 5.0V 0.5 0.6 V
VCC = 3.3V 0.3 0.4 V
START-UP
tSS Soft-start time  VFB  from 10% to 90%, tSS = 1ms setting 1 ms
 VFB  from 10% to 90%, tSS = 2ms setting 2 ms
 VFB  from 10% to 90%, tSS = 3ms setting 3 ms
tEN_DLY EN HIGH to start of switching delay no external bias on VCC 1300 2000 µs
REFERENCE VOLTAGE (FB)
VVOS_REG Output voltage regulation accuracy Internal feedabck configuration, TJ = 0°C to +85°C – 0.9 % +0.9 %
Internal feedback configuration – 1.25 % +1.25 %
VFB_REG Feedback regulation voltage External Feedback Configuration, TJ = 0°C to +85°C 498.5 501 503.5 mV
External Feedback Configuration 495 500 505 mV
IFB(LKG) FB input leakage current VFB = VFB_REG 250 nA
DIFFERENTIAL REMOTE SENSE AMPLIFIER
IGOSNS Leakage current out of GOS pin VGOS - VAGND = 100mV 80 µA
SWITCHING FREQUENCY
fSW(FCCM) Switching frequency, FCCM operation VVIN = 12V, VOUT = 3.3V, FSW = 600kHz, No load 510 600 690 kHz
VVIN = 12V, VOUT = 3.3V, FSW = 800kHz, No load 680 800 920 kHz
VVIN = 12V, VOUT = 3.3V, FSW = 1.0MHz, No load 850 1000 1150 kHz
VVIN = 12V, VOUT = 3.3V, FSW = 1.2MHz, No load 1020 1200 1380 kHz
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance VBOOT-SW = 5.0V 7.5 mΩ
VBOOT-SW = 3.3V 8.4 mΩ
RDSON(LS) Low-side MOSFET on-resistance VVCC = 5.0V 2.7 mΩ
VVCC = 3.3V 3.3 mΩ
tON(min) Minimum ON pulse width (1) 40 ns
tOFF(min) Minimum OFF pulse width (1) 150 ns
Output discharge resistor on SW pin VIN = 12V, VSW = 1V, power conversion disabled 75 Ω
IBOOT(LKG) Leakage current into BOOT pin VBOOT-SW = 3.3V, enabled, not switching. 23 30 µA
POWER GOOD
VPGTH(RISE_OV) Power-Good threshold FB rising, PG high to low 113% 116% 119%
VPGTH(RISE_UV) Power-Good threshold FB rising, PG low to high 89% 92.5% 95%
VPGTH(FALL_UV) Power-Good threshold FB falling, PG high to low 77% 80% 83%
tPG_DLY PG delay going from low to high during startup See timing diagram 1.1 1.5 ms
PG delay going from high to low 4 6.2 µs
IPG(LKG) PG pin leakage current when open drain output is high VPG = 4.5V 6 µA
PG pin output low-level voltage IPG = 7mA 500 mV
PG pin output low-level when VIN and VCC are low   VVIN = 0 V, VVCC = 0 V, VEN = 0 V, PG pulled up to 3.3 V through a 100-kΩ resistor 850 mV
PG pin output low-level when VIN and VCC are low   VVIN = 0 V, VVCC = 0 V, VEN = 0 V, PG pulled up to 3.3 V through a 10-kΩ resistor 1000 mV
OVERCURRENT PROTECTION
OC limit high clamp Valley current on LS FET, CFG3-5 = GND, 0Ω ≤ RILIM ≤ 4.32kΩ 19 21 23 A
ILS(OC) Low-side valley current limit (External Feedback Configuration)  Valley current on LS FET, RILIM = 5.25kΩ  15.5 17 18.5 A
Valley current on LS FET, RILIM = 10.5kΩ  7.5 8.5 9.5 A
Valley current on LS FET, RILIM = 20.0kΩ  3.8 4.5 5.2 A
RILIM ILIM pin resistance range 0 20 kΩ
ILS(OC) Low-side valley current limit (Internal Feeback Configuration) Valley current on LS FET, CFG3-5 = VCC, CFG1 = VCC 19 21 23 A
ILS(OC) Valley current on LS FET, CFG3-5 = VCC, CFG1 = GND 16 18 20 A
ILS(OC) Valley current on LS FET, CFG3-5 = VCC, CFG1 = Float 13 15 17 A
ILS(NOC) Low-side negative current limit  Sinking current limit on LS FET –9 –7.5 A
IZC Zero-cross detection current threshold to enter DCM, open loop VIN = 12V –750 mA
IZC(HYS) Zero-cross detection current threshold hysteresis after entering DCM, open loop VIN = 12V 1000 mA
OUTPUT OVP AND UVP
VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 113% 116% 119%
tOVPDLY OVP delay With 100mV overdrive 650 ns
VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 77% 80% 83%
tUVPDLY UVP filter delay 70 µs
Hiccup wait time Hiccup mode enabled 14 × tSS ms
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (1) Temperature rising 165 °C
TJ(HYS) Thermal shutdown hysteresis (1) 15 °C
(1) This parameter is provided for reference only, and do not consitute part of TI's published device specifications for purpose of TI's product warranty.