SLUSDO2C June 2020 β February 2021 UCC21540-Q1
PRODUCTION DATA
The total loss, P_{G}, in the gate driver subsystem includes the power losses of the UCC21540-Q1 (P_{GD}) and the power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not included in P_{G} and not discussed in this section.
P_{GD} is the key power loss which determines the thermal safety-related limits of the UCC21540-Q1, and it can be estimated by calculating losses from several components.
The first component is the static power loss, P_{GDQ}, which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. P_{GDQ} is measured on the bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and ambient temperature. and show the operating current consumption vs. operating frequency with no load. In this example, V_{VCCI} = 5 V and V_{VDD} = 12 V. The current on each power supply, with INA/INB switching from 0 V to 3.3 V at 100 kHz is measured to be I_{VCCI} β 2.5 mA, and I_{VDDA} = I_{VDDB} β 1.5 mA. Therefore, the P_{GDQ} can be calculated with
The second component is switching operation loss, P_{GDO}, with a given load capacitance which the driver charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, P_{GSW}, can be estimated with
where
If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail to the negative rail.
So, for this example application:
Q_{G} represents the total gate charge of the power transistor switching 480 V at 14 A provided by the datasheet, and is subject to change with different testing conditions. The UCC21540-Q1 gate driver loss on the output stage, P_{GDO}, is part of P_{GSW}. P_{GDO} will be equal to P_{GSW} if the external gate driver resistances are zero, and all the gate driver loss is dissipated inside the UCC21540-Q1. If there are external turn-on and turn-off resistances, the total loss will be distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however, it will be non-linear if the source/sink current is saturated. Therefore, P_{GDO} is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21540-Q1 gate driver loss can be estimated with:
Case 2 - Nonlinear Pull-Up/Down Resistor:
where
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the P_{GDO} will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21540-Q1 P_{GD}, is:
which is equal to 127 mW in the design example.