SLUSDO2C June   2020  β€“ February 2021 UCC21540-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     UCC21540-Q1 Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety-Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Switching Characteristics
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Minimum Pulses
    2. 8.2 Propagation Delay and Pulse Width Distortion
    3. 8.3 Rising and Falling Time
    4. 8.4 Input and Disable Response Time
    5. 8.5 Programmable Dead Time
    6. 8.6 Power-up UVLO Delay to OUTPUT
    7. 8.7 CMTI Testing
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 9.3.2 Input and Output Logic Table
      3. 9.3.3 Input Stage
      4. 9.3.4 Output Stage
      5. 9.3.5 Diode Structure in the UCC21540-Q1
    4. 9.4 Device Functional Modes
      1. 9.4.1 Disable Pin
      2. 9.4.2 Programmable Dead Time (DT) Pin
        1. 9.4.2.1 DT Pin Tied to VCCI
        2. 9.4.2.2 Connecting a Programming Resistor between DT and GND Pins
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing INA/INB Input Filter
        2. 10.2.2.2 Select Dead Time Resistor and Capacitor
        3. 10.2.2.3 Select External Bootstrap Diode and its Series Resistor
        4. 10.2.2.4 Gate Driver Output Resistor
        5. 10.2.2.5 Gate to Source Resistor Selection
        6. 10.2.2.6 Estimating Gate Driver Power Loss
        7. 10.2.2.7 Estimating Junction Temperature
        8. 10.2.2.8 Selecting VCCI, VDDA/B Capacitor
          1. 10.2.2.8.1 Selecting a VCCI Capacitor
          2. 10.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 10.2.2.8.3 Select a VDDB Capacitor
        9. 10.2.2.9 Application Circuits with Output Stage Negative Bias
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Component Placement Considerations
      2. 12.1.2 Grounding Considerations
      3. 12.1.3 High-Voltage Considerations
      4. 12.1.4 Thermal Considerations
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Gate Driver Output Resistor

The external gate driver resistors, RON/ROFF, are used to:

  • Limit ringing caused by parasitic inductances/capacitances.
  • Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
  • Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
  • Reduce electromagnetic interference (EMI).

As mentioned in Section 9.3.4, the UCC21540-Q1 has a pull-up structure with a P-channel MOSFET and an additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak source current can be predicted with:

Equation 3. GUID-6877A8CE-DBF8-447F-B30C-D314BC913257-low.gif
Equation 4. GUID-19A37802-CEAA-453E-BAC2-C14F090F2395-low.gif

where

  • RON: External turn-on resistance.
  • RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
  • IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the calculated value based on the gate drive loop resistance.

In this example:

Equation 5. GUID-A1AF90AD-4B22-4C9D-B205-D59028C8A41E-low.gif
Equation 6. GUID-953675CE-D000-4D09-8307-42A0187F7388-low.gif

Therefore, the high-side and low-side peak source current is 2.3 A and 2.5 A respectively. Similarly, the peak sink current can be calculated with:

Equation 7. GUID-5A242C82-AB89-4BC9-B2F5-78C38D5EF85F-low.gif
Equation 18. GUID-E57411C7-889C-4D8D-BFA5-77E163D3137B-low.gif

where

  • ROFF: External turn-off resistance, ROFF=0 in this example;
  • VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an MSS1P4.
  • IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated value based on the gate drive loop resistance.

In this example,

Equation 9. GUID-BE1F5611-8D2D-4483-92AB-58C54F48E699-low.gif
Equation 10. GUID-31FB1D8C-A897-45F1-ACFC-450E39AE43B3-low.gif

Therefore, the high-side and low-side peak sink current is 5.0 A and 5.4A respectively.

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the parasitic ringing period.

Failure to control OUTx voltage to less than the Absolute Maximum Ratings in the datasheet (including transients) may result in permanent damage to the device in certain cases. To reduce excessive gate ringing, it is recommended to use a ferrite bead near the gate of the FET. External clamping diodes can also be added in the case of extended overshoot/undershoot, in order to clamp the OUTx voltage to the VDDx and VSSx voltages.