SLUSD37E October 2017 – November 2019 UCC28056
The integrator response of the plant provides a gain roll off of –20dB/decade and introduces a phase lag of 90°. A simple integrating compensation network provides unacceptable phase margin because it introduces a second 90° of phase lag into the voltage loop. To ensure adequate phase margin, use a type 2 compensation network to provide the desired phase boost a the gain cross-over frequency. Equation 84 describes the mall-signal gain of the error amplifier and type 2 compensation network.
may also be expressed as follows:
For maximum phase Boost at the gain cross-over frequency, compensator design proceeds by placing the pole and zero an equal distance above and below the gain cross-over frequency (fB) on the Bode plot. Because the frequency axis is logarithmic this yields the following pole (fP) and zero (fZ) frequencies:
Phase margin of the loop is equal to the phase boost provided by the type 2 compensator, because the underlying integrator characteristics of the plant and compensator combine to provide 180° of phase lag. To achieve the desired phase margin (ΦPM) at fB the separation between the pole and zero frequencies may be found by substituting Equation 92 and Equation 93 into Equation 85, and solving for K in terms of the phase boost angle.
The next step is to select the desired phase margin. A typical phase margin range 45° to 75°. For this example design a target phase margin of 65° is selected.
The next step is to determine the loop gain cross-over frequency (fB). A faster loop, results in more twice Line frequency ripple on the COMP pin voltage, leading to increased Line current distortion.
Begin by setting a target of 1% third harmonic distortion due to twice Line frequency COMP voltage ripple. To achieve this target, the twice Line frequency COMP pin ripple must be less than 2% of the DC value during steady-state full power operation. The design proceeds by selecting the loop gain cross-over frequency (fB) that ensures twice Line frequency COMP pin ripple amplitude does not exceed 2% of its DC level.
Use Equation 97 to calculate twice Line frequency voltage ripple amplitude across the output capacitor.
The output voltage ripple amplitude must be attenuated by the feedback network to meet our target of 2% ripple amplitude on the COMP pin voltage.
Equation 100 describes unity at the gain cross-over frequency.