SLUSD37E October   2017  – November 2019 UCC28056


  1. Features
  2. Applications
  3. Description
    1.     No Load Power
      1.      Device Images
        1.       Simplified Application
  4. Revision History
  5. Device Comparison Tables
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CrM/DCM Control Principle
      2. 8.3.2 Line Voltage Feed-Forward
        1. Peak Line Voltage Detection
      3. 8.3.3 Valley Switching and CrM/DCM Hysteresis
        1. Valley Delay Adjustment
      4. 8.3.4 Transconductance Amplifier with Transient Speed-up Function
      5. 8.3.5 Faults and Protections
        1. Supply Undervoltage Lockout
        2. Two Level Over-Current Protection
          1. Cycle-by-Cycle Current Limit Ocp1
          2. Ocp2 Gross Over-Current or CCM Protection
        3. Output Over-Voltage Protection
          1. First Level Output Over-Voltage Protection (Ovp1)
          2. Second Level Over-Voltage Protection (Ovp2)
        4. Thermal Shutdown Protection
        5. Line Under-Voltage or Brown-In
      6. 8.3.6 High-Current Driver
    4. 8.4 Controller Functional Modes
      1. 8.4.1 Burst Mode Operation
      2. 8.4.2 Soft Start
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Power Stage Design
          1. Boost Inductor Design
          2. Boost Switch Selection
          3. Boost Diode Selection
          4. Output Capacitor Selection
        3. ZCD/CS Pin
          1. Voltage Spikes on the ZCD/CS pin Waveform
        4. VOSNS Pin
        5. Voltage Loop Compensation
          1. Plant Model
          2. Compensator Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 VOSNS Pin
      2. 11.1.2 ZCD/CS Pin
      3. 11.1.3 VCC Pin
      4. 11.1.4 GND Pin
      5. 11.1.5 DRV Pin
      6. 11.1.6 COMP Pin
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Compensator Design

The integrator response of the plant provides a gain roll off of –20dB/decade and introduces a phase lag of 90°. A simple integrating compensation network provides unacceptable phase margin because it introduces a second 90° of phase lag into the voltage loop. To ensure adequate phase margin, use a type 2 compensation network to provide the desired phase boost a the gain cross-over frequency. Equation 84 describes the mall-signal gain of the error amplifier and type 2 compensation network.

Equation 84. UCC28056 eq-84.gif

may also be expressed as follows:

Equation 85. UCC28056 eq-85.gif


    Equation 86. UCC28056 eq-86.gif
    Equation 87. UCC28056 eq-87.gif
    Equation 88. UCC28056 eq-88.gif

Rearranging Equation 86, Equation 87 and Equation 88 yields:

Equation 89. UCC28056 eq-89.gif
Equation 90. UCC28056 eq-90.gif
Equation 91. UCC28056 eq-91.gif

For maximum phase Boost at the gain cross-over frequency, compensator design proceeds by placing the pole and zero an equal distance above and below the gain cross-over frequency (fB) on the Bode plot. Because the frequency axis is logarithmic this yields the following pole (fP) and zero (fZ) frequencies:

Equation 92. UCC28056 eq-92.gif
Equation 93. UCC28056 eq-93.gif

Phase margin of the loop is equal to the phase boost provided by the type 2 compensator, because the underlying integrator characteristics of the plant and compensator combine to provide 180° of phase lag. To achieve the desired phase margin (ΦPM) at fB the separation between the pole and zero frequencies may be found by substituting Equation 92 and Equation 93 into Equation 85, and solving for K in terms of the phase boost angle.

Equation 94. UCC28056 eq-94.gif

The next step is to select the desired phase margin. A typical phase margin range 45° to 75°. For this example design a target phase margin of 65° is selected.

Equation 95. UCC28056 eq-95.gif
Equation 96. UCC28056 eq-96.gif

The next step is to determine the loop gain cross-over frequency (fB). A faster loop, results in more twice Line frequency ripple on the COMP pin voltage, leading to increased Line current distortion.

Begin by setting a target of 1% third harmonic distortion due to twice Line frequency COMP voltage ripple. To achieve this target, the twice Line frequency COMP pin ripple must be less than 2% of the DC value during steady-state full power operation. The design proceeds by selecting the loop gain cross-over frequency (fB) that ensures twice Line frequency COMP pin ripple amplitude does not exceed 2% of its DC level.

Use Equation 97 to calculate twice Line frequency voltage ripple amplitude across the output capacitor.

Equation 97. UCC28056 eq-97.gif

The output voltage ripple amplitude must be attenuated by the feedback network to meet our target of 2% ripple amplitude on the COMP pin voltage.

Equation 98. UCC28056 eq-98.gif

Equation 99 simplifies Equation 98.

Equation 99. UCC28056 eq-99.gif


  • 2 x fLine >> fP
  • 2 x fLine >> fZ

Equation 100 describes unity at the gain cross-over frequency.

Equation 100. UCC28056 eq-100.gif

Equation 100 can also be expressed as shown in Equation 101.

Equation 101. UCC28056 eq-101.gif

Calculate the pole and zero frequencies using Equation 92 and Equation 93. Then determine the compensation component values using Equation 89, Equation 90 and Equation 91.

Equation 102. UCC28056 eq-102.gif
Equation 103. UCC28056 eq-103.gif
Equation 104. UCC28056 eq-104.gif
Equation 105. UCC28056 eq-105.gif
Equation 106. UCC28056 eq-106.gif
UCC28056 BodeGain.gifFigure 31. Gain vs Frequency
UCC28056 BodePhase.gifFigure 32. Phase vs Frequency