SLUSD37E October   2017  β€“ November 2019 UCC28056

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     No Load Power
      1.      Device Images
        1.       Simplified Application
  4. Revision History
  5. Device Comparison Tables
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CrM/DCM Control Principle
      2. 8.3.2 Line Voltage Feed-Forward
        1. 8.3.2.1 Peak Line Voltage Detection
      3. 8.3.3 Valley Switching and CrM/DCM Hysteresis
        1. 8.3.3.1 Valley Delay Adjustment
      4. 8.3.4 Transconductance Amplifier with Transient Speed-up Function
      5. 8.3.5 Faults and Protections
        1. 8.3.5.1 Supply Undervoltage Lockout
        2. 8.3.5.2 Two Level Over-Current Protection
          1. 8.3.5.2.1 Cycle-by-Cycle Current Limit Ocp1
          2. 8.3.5.2.2 Ocp2 Gross Over-Current or CCM Protection
        3. 8.3.5.3 Output Over-Voltage Protection
          1. 8.3.5.3.1 First Level Output Over-Voltage Protection (Ovp1)
          2. 8.3.5.3.2 Second Level Over-Voltage Protection (Ovp2)
        4. 8.3.5.4 Thermal Shutdown Protection
        5. 8.3.5.5 Line Under-Voltage or Brown-In
      6. 8.3.6 High-Current Driver
    4. 8.4 Controller Functional Modes
      1. 8.4.1 Burst Mode Operation
      2. 8.4.2 Soft Start
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Power Stage Design
          1. 9.2.2.2.1 Boost Inductor Design
          2. 9.2.2.2.2 Boost Switch Selection
          3. 9.2.2.2.3 Boost Diode Selection
          4. 9.2.2.2.4 Output Capacitor Selection
        3. 9.2.2.3 ZCD/CS Pin
          1. 9.2.2.3.1 Voltage Spikes on the ZCD/CS pin Waveform
        4. 9.2.2.4 VOSNS Pin
        5. 9.2.2.5 Voltage Loop Compensation
          1. 9.2.2.5.1 Plant Model
          2. 9.2.2.5.2 Compensator Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 VOSNS Pin
      2. 11.1.2 ZCD/CS Pin
      3. 11.1.3 VCC Pin
      4. 11.1.4 GND Pin
      5. 11.1.5 DRV Pin
      6. 11.1.6 COMP Pin
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VCCStart Turn-on threshold VCC Rising 10.65 11 V
VCCStop Turn-off threshold VCC Falling 8.5 8.85 9.2 V
VCCHyst UVLO Hysteresis (VCCStart - VCCStop) (1) 1.5 V
TUVLOBlk Turn-OFF Blanking Time 27 35 42 µs
SUPPLY CURRENT
ICC_Startup Current consumption before startup VCC = VCCStart-200mV, TA < 110℃ 46 µA
ICC_FAULT Current consumption during fault condition VCC = 12V 130 µA
ICC_BSTOFF Current consumption during Burst OFF period VCC = 12V 132 µA
ICC_RUN Operating current with DRV pin unloaded VCC = 12V 1.8 2.2 mA
GATE DRIVE
VDRLow DRV output low voltage IDR = 100mA 0.9 V
VDRHigh DRV output voltage high level, limited VCC = 25V, IDR = -10mA 10 13.7 15 V
VDRHighMin DRV minimum high voltage level VCC = VCCStop + 200 mV, IDR = -8mA 8 V
RDRH DRV, Pull-up resistance TA = -40°C to 125°C, IDR = -8mA, VCC=12V 9.7 16 Ω
RDRL DRV, Pull-down resistance TA = -40°C to 125°C, IDR = 100mA 2.0 4.6 9 Ω
tR Rise Time CLOAD=1nF, DRV=1V to 6V, VCC=12V 10 34 61 ns
tF Fall Time CLOAD=1nF, DRV=6V to 1V, VCC=12V 4 15 40 ns
Isource Source peak current on DRV Pin (1) -0.7 A
Isink Sink peak current on DRV Pin (1) 1 A
RDG0 DRV to GND resistance value to select TZCDR0 (1) 130 200
RDG1 DRV to GND resistance value to select TZCDR1 (1) 81.18 82 82.82
RDG2 DRV to GND resistance value to select TZCDR2 (1) 61.38 62 62.62
RDG3 DRV to GND resistance value to select TZCDR3 (1) 42.57 43 43.43
RDG4 DRV to GND resistance value to select TZCDR4 (1) 26.73 27 27.27
RDG5 DRV to GND resistance value to select TZCDR5 (1) 17.82 18 18.18
RDG6 DRV to GND resistance value to select TZCDR6 (1) 12.87 13 13.13
RDG7 DRV to GND resistance value to select TZCDR7 (1) 9 9.1 9.2
TDGSmpl Time needed to detect RDG value. TA < 85℃ 3.95 4.4 4.95 ms
VDGClmp Maximum voltage that will be applied on DRV pin while detecting RDG value. 1 1.05 1.1 V
Error Amplifier
VOSReg Feedback voltage reference 2.45 2.5 2.55 V
IOSBias ISNS pin bias current VOS = VOSReg -100 100 nA
gM Error Amplifier Transconductance Gain |VOS-VOSReg| < DSuThs 50 µS
gMNL Error Amplifier Transconductance Gain for large error |VOS-VOSReg| > DSuThs 300 µS
DSuThs Non-Linear Gain Threshold 67 mV
RCODisch Internal COMP to GND resistance when in STOPb state. 4.3 5 5.7
VCOClmp COMP pin internal high clamp voltage 5.5 5.6 5.71 V
VCOSat COMP pin internal low clamp voltage (1) 0 V
ICOMin COMP Maximum Source Current -120 µA
ICOMax COMP Maximum Sink Current 120 µA
Line Voltage Feed-Forward
THLinMax Line peak sampling window (1) While switching 11 12.3 13.6 ms
VFF0Rise Comparator rising threshold switching from GFF0 to GFF1 (1) 0.348 V
VFF1Rise Comparator rising threshold switching from GFF1 to GFF2 (1) 0.406 V
VFF2Rise Comparator rising threshold switching from GFF2 to GFF3 (1) 0.473 V
VFF3Rise Comparator rising threshold switching from GFF3 to GFF4 (1) 0.552 V
VFF4Rise Comparator rising threshold switching from GFF4 to GFF5 (1) 0.644 V
VFF5Rise Comparator rising threshold switching from GFF5 to GFF6 (1) 0.751 V
VFF6Rise Comparator rising threshold switching from GFF6 to GFF7 (1) 0.875 V
VFF0Fall Comparator falling threshold switching from GFF1 to GFF0 (1) Peak value of VInSynth within THLinMax Window 0.331 V
VFF1Fall Comparator falling threshold switching from GFF2 to GFF1 (1) Peak value of VInSynth within THLinMax Window 0.386 V
VFF2Fall Comparator falling threshold switching from GFF3 to GFF2 (1) Peak value of VInSynth within THLinMax Window 0.45 V
VFF3Fall Comparator falling threshold switching from GFF4 to GFF3 (1) Peak value of VInSynth within THLinMax Window 0.524 V
VFF4Fall Comparator falling threshold switching from GFF5 to GFF4 (1) Peak value of VInSynth within THLinMax Window 0.612 V
VFF5Fall Comparator falling threshold switching from GFF6 to GFF5 (1) Peak value of VInSynth within THLinMax Window 0.713 V
VFF6Fall Comparator falling threshold switching from GFF7 to GFF6 (1) Peak value of VInSynth within THLinMax Window 0.832 V
GFF0 Line Feed-Forward gain level 0 (1) 1
GFF1 Line Feed-Forward gain level 1 (1) 0.735
GFF2 Line Feed-Forward gain level 2 (1) 0.541
GFF3 Line Feed-Forward gain level 3 (1) 0.398
GFF4 Line Feed-Forward gain level 4 (1) 0.292
GFF5 Line Feed-Forward gain level 5 (1) 0.215
GFF6 Line Feed-Forward gain level 6 (1) 0.158
GFF7 Line Feed-Forward gain level 7 (1) 0.116
Maximum ON Time
TONMAX0 Maximum ON time when GFF = GFF0 12.1 12.8 13.2 µs
TONMAX1 Maximum ON time when GFF = GFF1 10.42 10.98 11.28 µs
TONMAX2 Maximum ON time when GFF = GFF2 8.85 9.41 9.64 µs
TONMAX3 Maximum ON time when GFF = GFF3 7.59 8.07 8.32 µs
TONMAX4 Maximum ON time when GFF = GFF4 6.52 6.92 7.18 µs
TONMAX5 Maximum ON time when GFF = GFF5 5.56 5.93 6.16 µs
TONMAX6 Maximum ON time when GFF = GFF6 4.73 5.09 5.28 µs
TONMAX7 Maximum ON time when GFF = GFF7 4.07 4.36 4.57 µs
Burst Mode Operation   See Device Comparison Table
Zero Current Detection and Valley Synch
VZcdVinHyst ZcdVin Comparator hysteresis (1) 12 19 26 mV
TDCHVinMin ZcdVin Comparator blanking from DRV falling edge (1) 250 358 467 ns
TZCDTo If no negative transitions on Vin comparator for this period then do not wait for valleys 2.035 2.4 3.0 µs
TZCDR0 Minimum ZCD to DRV delay. From VZC < VInSynth to DRV = 6V, CDR = 1nF, Fres = 1.2MHz, RDG = RDG0 170 235 ns
ΔTZCDR1 TZCDR1 = TZCDR0 + ΔTZCDR1 (1) RDG = RDG1 34.6 45.5 58.5 ns
ΔTZCDR2 TZCDR2 = TZCDR0 + ΔTZCDR2 (1) RDG = RDG2 76 90 107 ns
ΔTZCDR3 TZCDR3 = TZCDR0 + ΔTZCDR3 (1) RDG = RDG3 114 130 147 ns
ΔTZCDR4 TZCDR4 = TZCDR0 + ΔTZCDR4 (1) RDG = RDG4 157 175 193 ns
ΔTZCDR5 TZCDR5 = TZCDR0 + ΔTZCDR5 (1) RDG = RDG5 229 255 281 ns
ΔTZCDR6 TZCDR6 = TZCDR0 + ΔTZCDR6 (1) RDG = RDG6 301 335 369 ns
ΔTZCDR7 TZCDR7 = TZCDR0 + ΔTZCDR7 (1) RDG = RDG7 373 415 457 ns
VDDAmpl Amplitude of 500 kHz sinewave signal on ZCD/CS pin needed to trigger knee detector 25 mV
TDCHDDMin Knee point detector blanking period (1) Measured from falling edge of DRV pulse 1.5 µs
Fault Protection
TLongFlt Long Fault Duration (1) 1 s
Line Brown-In Protection
VZCBoRise Brown-out Protection Threshold when in Stopb state Peak cycle average voltage on ZCD/CS Pin. 0.282 0.3 0.318 V
IZCBias ZCD/CS Pin Bias Current (1) VZC = VZCBoFall -100 100 nA
Over-Current Protection
VZCOcp1 ZCD/CS First Level over-current protection threshold 450 500 550 mV
VZCOcp2 ZCD/CS Second Level over-current protection threshold 670 750 825 mV
TOcp1Blk ZCD/CS blanking time from DRV rising edge to Enable Ocp1 Comparator Output (1) 450 ns
TOcp2Blk ZCD/CS blanking time from DRV rising edge to Enable Ocp2 Comparator Output (1) 250 ns
TOcpDrvDel ZCD/CS crossing VOcpxTh to DRV falling edge. 56 120 ns
TDCHMax0 Max duration of TDCHb state if no ZCD signal detected. After no OCPx Events (1) 250 µS
TDCHMax1 Max duration of TDCHb state if no ZCD signal detected. After one OCPx Events (1) 500 µS
TDCHMax2 Max duration of TDCHb state if no ZCD signal detected. After two consecutive OCPx Events (1) 1000 µS
Output Over-Voltage Protection    See Device Comparison Table
Thermal Protection
TTSDRise Thermal Shutdown Rising Threshold (1) While switching 135 145 155 °C
TTSDFall Thermal Shutdown Falling Threshold (1) While not switching 95 105 115 °C
TTSDHyst TTSDRise - TTSDFall (1) 38 40 42 °C
Not tested in production. Ensured by design.