SLUSD37E October 2017 – November 2019 UCC28056
The UCC28056 delivers maximum efficiency when controlling power stages that have widely differing natural resonant frequencies. The application achieves this efficiency because the designer externally programs the delay between the ZcdVIn comparator crossing and the rising edge of DRV (TZCDR). Ideal valley switching for different power stage designs that may have very different natural resonant frequencies.
The TZCDR delay can be set to one of eight different values (TZCDR0 – TZCDR7) by setting the value of a resistor (RDG) connected externally between the DRV and GND pins. During the startup period or when recovering from a long fault, the controller transitions from the Stopb state to the RDGRdb state and then to the BstOffb state. While in the RDGRdb state, an internal current source (IDG) transitions to the DRV pin. The the voltage that results from this current determines the appropriate TZCDR delay. The controller uses this delay period for all valley switching operation until a long fault causes the controller to return to the Stopb state.
After entering its RDGRdb state, the controller waits for TDGSmpl before reading the pin voltage. To ensure that the controller consistently detects the external resistance value correctly, do not allow the total external capacitance connected between the DRV and GND pins to exceed 12 nF.