SLUSD37E October   2017  – November 2019 UCC28056


  1. Features
  2. Applications
  3. Description
    1.     No Load Power
      1.      Device Images
        1.       Simplified Application
  4. Revision History
  5. Device Comparison Tables
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CrM/DCM Control Principle
      2. 8.3.2 Line Voltage Feed-Forward
        1. Peak Line Voltage Detection
      3. 8.3.3 Valley Switching and CrM/DCM Hysteresis
        1. Valley Delay Adjustment
      4. 8.3.4 Transconductance Amplifier with Transient Speed-up Function
      5. 8.3.5 Faults and Protections
        1. Supply Undervoltage Lockout
        2. Two Level Over-Current Protection
          1. Cycle-by-Cycle Current Limit Ocp1
          2. Ocp2 Gross Over-Current or CCM Protection
        3. Output Over-Voltage Protection
          1. First Level Output Over-Voltage Protection (Ovp1)
          2. Second Level Over-Voltage Protection (Ovp2)
        4. Thermal Shutdown Protection
        5. Line Under-Voltage or Brown-In
      6. 8.3.6 High-Current Driver
    4. 8.4 Controller Functional Modes
      1. 8.4.1 Burst Mode Operation
      2. 8.4.2 Soft Start
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Power Stage Design
          1. Boost Inductor Design
          2. Boost Switch Selection
          3. Boost Diode Selection
          4. Output Capacitor Selection
        3. ZCD/CS Pin
          1. Voltage Spikes on the ZCD/CS pin Waveform
        4. VOSNS Pin
        5. Voltage Loop Compensation
          1. Plant Model
          2. Compensator Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 VOSNS Pin
      2. 11.1.2 ZCD/CS Pin
      3. 11.1.3 VCC Pin
      4. 11.1.4 GND Pin
      5. 11.1.5 DRV Pin
      6. 11.1.6 COMP Pin
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Capacitor Selection

Power drawn by the PFC stage from the Line supply may be represented by the following expression.

Equation 39. UCC28056 eq-39.gif

Assuming a typical application, with constant load power, for some parts of the Line cycle excess power is drawn from the supply and stored in the output capacitor. In other parts of the Line cycle load power exceeds input power and this deficit must be supplied from the output capacitor. This process of energy transfer to an from the output capacitor necessarily results in twice Line frequency output voltage ripple. The amplitude of this twice Line frequency ripple depends only upon the ratio POut/COut and the Line frequency.

Equation 40. UCC28056 eq-40.gif

Choose an output capacitor value by prioritizing one of a number of application requirements:

  • Twice Line frequency output ripple voltage at maximum load.
  • Output voltage hold-up time after the Line supply has been disconnected.
  • Output voltage deviation as a result of a transient load step.

For this design example assume that the twice Line frequency output ripple voltage amplitude is less than 3% of its regulation level. The POutMax/COut ratio required to achieve this can be calculated using Equation 41

Equation 41. UCC28056 eq-41.gif

Use Equation 42 to calculate the required capacitance value for this 165-W example design.

Equation 42. UCC28056 eq-42.gif

For best Line current total harmonic distortion (THD), the maximum output voltage ripple amplitude must satisfy the condition presented in Equation 43. Satisfying this condition ensures that the error amplifier non-linear gain does not activate due to extremes of the output voltage ripple.

Equation 43. UCC28056 eq-43.gif

Use Equation 44 to calculate the maximum RMS ripple current flowing in the output capacitor.

Equation 44. UCC28056 eq-44.gif

This current flowing into the output capacitor includes a switching frequency component (ICOutRMSHF) and a twice Line frequency ripple component (ICOutRMSLF).

Equation 45. UCC28056 eq-45.gif
Equation 46. UCC28056 eq-46.gif

Electrolytic capacitors typically have a ripple current rating at twice Line frequency (120 Hz) and a different ripple current rating at switching frequency (100 kHz). These ratings reflect the fact that the capacitor ESR is higher at twice Line frequency and hence ripple current at this frequency leads to higher power loss than the same amplitude of switching frequency ripple. Consider the equivalent high-frequency ripple current flowing in the capacitor in order to select the correct capacitor.

Equation 47. UCC28056 eq-47.gif

The parameter KHLF is the ratio of high frequency to low frequency RMS ripple current rating for the particular capacitor series to be used.

Equation 48. UCC28056 eq-48.gif

In this example design, for reasons of size and rating, two 68-µF, 450 V capacitors are selected from Rubycon BXW series (450BXW68MEFC12.5X45), connected in parallel. In this way, both the capacitance value requirement and ripple current rating are met with some additional margin.

Equation 49. UCC28056 eq-49.gif
Equation 50. UCC28056 eq-50.gif