SLUSD37E October 2017 – November 2019 UCC28056
UCC28056 internally reconstructs the input voltage waveform for the purpose of Peak Line voltage sensing and Zero Current Detection (ZCD). In DCM or CrM mode the cycle average voltage across the Boost inductor must be zero. UCC28056 generates an internal representation of input voltage by extracting the Drain waveform from the ZCD/CS pin waveform and filtering it to extract the average Drain voltage across a switching cycle (VInSyn(θ))
The digital peak detector selects the value of GFF based upon the highest comparator threshold crossed over the period THLinMax . The switch to a higher GFF value is implemented as soon as the corresponding threshold is crossed. The switch to a lower GFF value is only implemented once the period THLinMax expires and the peak detector has captured the Line voltage peak. The THLinMax timer is not synchronized to the Line operating frequency.
Prior to the start of switching operation, at power - up or after a Burst - OFF period, the ZCD/CS pin voltage is sampled and used to select the appropriate starting GFF level. This method assumes that the input rectifier and capacitor after the rectifier bridge have captured the peak Line voltage during the period of no switching.