SLUSD37E October   2017  – November 2019 UCC28056


  1. Features
  2. Applications
  3. Description
    1.     No Load Power
      1.      Device Images
        1.       Simplified Application
  4. Revision History
  5. Device Comparison Tables
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CrM/DCM Control Principle
      2. 8.3.2 Line Voltage Feed-Forward
        1. Peak Line Voltage Detection
      3. 8.3.3 Valley Switching and CrM/DCM Hysteresis
        1. Valley Delay Adjustment
      4. 8.3.4 Transconductance Amplifier with Transient Speed-up Function
      5. 8.3.5 Faults and Protections
        1. Supply Undervoltage Lockout
        2. Two Level Over-Current Protection
          1. Cycle-by-Cycle Current Limit Ocp1
          2. Ocp2 Gross Over-Current or CCM Protection
        3. Output Over-Voltage Protection
          1. First Level Output Over-Voltage Protection (Ovp1)
          2. Second Level Over-Voltage Protection (Ovp2)
        4. Thermal Shutdown Protection
        5. Line Under-Voltage or Brown-In
      6. 8.3.6 High-Current Driver
    4. 8.4 Controller Functional Modes
      1. 8.4.1 Burst Mode Operation
      2. 8.4.2 Soft Start
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Power Stage Design
          1. Boost Inductor Design
          2. Boost Switch Selection
          3. Boost Diode Selection
          4. Output Capacitor Selection
        3. ZCD/CS Pin
          1. Voltage Spikes on the ZCD/CS pin Waveform
        4. VOSNS Pin
        5. Voltage Loop Compensation
          1. Plant Model
          2. Compensator Design
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 VOSNS Pin
      2. 11.1.2 ZCD/CS Pin
      3. 11.1.3 VCC Pin
      4. 11.1.4 GND Pin
      5. 11.1.5 DRV Pin
      6. 11.1.6 COMP Pin
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Custom Design With WEBENCH® Tools
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


An external divider network attached to the ZCD/CS pin transfers both the attenuated Drain voltage waveform (VDS) and the current sense signal (VCS) into the controller. This transfer is possible because the current sense signal requires observation only when the switch is ON and the VDS signal is close to zero. While the Drain voltage waveform requires sensing only when the switch is OFF and the current sense signal is close to zero.

Equation 51. UCC28056 eq-51.gif

Equation 52 describes the attenuated Drain voltage during the on-time period when the MOSFET is switched ON.

Equation 52. UCC28056 eq-52.gif

The ON state resistance of the MOSFET (RDSON) typically has a similar value to the current sense resistor (RCS). The attenuation of the divider (ZZC1, ZZC2) is 1/401 and hence the second term of Equation 52 may be neglected.

Equation 53. UCC28056 eq-53.gif

Hence the required current sense resistor value can be calculated from the maximum peak inductor current obtained in

Outside the TON period, when the MOSFET is switched OFF, the current flowing through the current sense resistor is close to zero. In this case Equation 51 may be expressed as follows.

Equation 54. UCC28056 eq-54.gif

UCC28056 prevents the start of a new switching cycle until increasing negative slope is detected on the ZCD/CS pin voltage waveform. The increasing negative slope indicates that the inductor current has fallen to zero so the output diode is already OFF. Turn-ON switching loss is further reduced by synchronizing the start of each new switching cycle with a minimum, or valley, on the Drain waveform.

In theory, a simple resistor divider can be used to attenuate the Drain voltage waveform fed into the ZCD/CS pin. In practice, the parasitic capacitance associated with the PCB traces and the ZCD/CS pin filter the attenuated signal and introduce phase shift. The resulting distortion and phase shift negatively impact the ability of the part to synchronize to the zero inductor current transitions. The problem is compounded by the need to limit power dissipation in the resistive divider, which dictates the use of high resistance values, and increased filtering of the attenuated signal.

Add a capacitor divider in parallel with the resistor divider in order to use of high value resistors without introducing filtering and associated phase shift. In this case, ensure that the reactive divider ratio is equal to the resistor divider ratio.

Equation 55. UCC28056 eq-55.gif


Equation 56. UCC28056 eq-56.gif

There are number of internal voltage thresholds driven by the attenuated Drain voltage signal supplied to the ZCD/CS pin. These include Brown-Out (VZCBoRise), Line feed-forward (VFFxRise, VFFxFall) and second output over-voltage (VOvp2Th). The same external divider ratio (KZC) drives all of these thresholds. Scope to vary the attenuation ratio specified is limited because it impacts all of these thresholds in unison.

Equation 57. UCC28056 eq-57.gif
Equation 58. UCC28056 eq-58.gif

The controller infers Line voltage from the switching cycle average voltage on the Drain node. Neglecting any resistive voltage drop in the Boost inductor this must be equal to the voltage supplied from the input rectifier, provided the Boost inductor current returns to zero at the end of each cycle (TM/CrM/DCM). Voltage drops in the input rectifier bridge and EMI filter stage cause an error between predicted and measured threshold values. An internal peak detector determines the peak input voltage across a Line half-cycle. Equation 58 above converts this peak value to an RMS quantity, but assumes an ideal sinusoidal Line supply

Equation 59 calculates the output voltage required to trigger the second output overvoltage comparator (Ovp2).

Equation 59. UCC28056 eq-59.gif

This parameter is observed via the Drain waveform, voltage drops in the Boost Diode and series NTC resistor, causes the Ovp2 comparator to trip at a lower output voltage level.

Power dissipation in the Drain sensing resistor divider chain reaches its highest value during the Burst OFF condition. During the Burst OFF condition, the Drain voltage approximates a DC voltage equal to the Line voltage peak. This approximation assumes the time constant CIN × (RZC1+ RZC2) is long compared with a Line half-period. Under no-load conditions, the Burst OFF duty cycle is high therefore maximum power dissipation in the Drain sensing resistor divider chain, occurs at high Line and no-load, as described in Equation 60.

Equation 60. UCC28056 eq-60.gif

Equation 61 calculates the maximum value of RZC1 c, allowing a budget of 1% error due to input bias current (IZCBias), on the lowest voltage threshold (VZCBoRise).

Equation 61. UCC28056 eq-61.gif

The upper resistor in the divider chain (RZC1) must withstand the peak output voltage under a surge test. For a rugged solution, the resistor(s) in this location must have a voltage rating above the avalanche rating of the Boost MOSFET. This design uses a series chain of three 1206, SMT, 3.24 MΩ resistors for this location, which yields DC voltage withstand capability above 600 V.

Equation 62. UCC28056 eq-62.gif
Equation 63. UCC28056 eq-63.gif

Use Equation 60 to calculate the power dissipation in the ZCD/CS pin divider resistors.

Equation 64. UCC28056 eq-64.gif

Once arranged on the PCB, the resistor divider circuit has some parasitic capacitance across both the upper (RZC1) and lower (RZC2) resistors. Experience suggests a parasitic capacitance (CZC1) of approximately 0.1 pF across resistor RZC1, when it is made up of three 1206 SMT components, assuming a compact PCB layout. In theory this parasitic capacitance could be used to form the entire value of CZC1 and an appropriate value of CZC2 added to achieve the ratio required by Equation 56. In practice most designers choose to add an explicit capacitor in this location to improve tolerance to small changes in layout, such as may occur when connecting oscilloscope probes. Ensure the time constant for the divider does not extend over many switching cycles. This limitation ensures that Line surge or system ESD transient events may disturb the ZCD/CS pin DC level but does not persist over an excessive number of switching cycles.

Select a single 10-pF, 1000-V, 0805 SMT capacitor with 5% tolerance.

Equation 65. UCC28056 eq-65.gif

Use Equation 66 calculate the lower divider capacitor value.

Equation 66. UCC28056 eq-66.gif

In practice, once the final PCB layout is complete, adjust the lower capacitor value to account for parasitic capacitances present on the PCB. Consider both the Drain and ZCD/CS pin waveforms and adjust the lower capacitance value (CZC2) until the value allows the required ratio in signal amplitude. Use a low capacitance probe for the ZCD/CS pin connection. Figure 28, Figure 29 and Figure 30 present the type of waveforms that occur during this tuning process.

UCC28056 reduce Czc2.gif
Figure 28. Amplitude VZC < (VDS/401). Reduce CZC2 Capacitance
UCC28056 increase Czc2.gif
Figure 30. Amplitude VZC > (VDS/401). Increase CZC2 Capacitance
UCC28056 correct Czc2.gif
Figure 29. Amplitude VZC = (VDS/401). Correct CZC2 Capacitance