JAJSBK7H January 2012 – February 2018 DS125DF410
The DS125DF410 performs its clock and data recovery function by detecting the bit transitions in the incoming data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit transitions. This process produces a recovered clock with greatly reduced jitter at jitter frequencies outside the bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the DS125DF410 in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter budget for the system.
The DS125DF410 uses the 25 MHz reference to determine the coarse tuning setting for its internal VCO. On power-up, on CDR reset, and when the DS125DF410 loses lock and cannot re-acquire lock after four attempts, the 25 MHz reference is used to calibrate the VCO frequency. The required VCO frequency is set by using the rate/subrate settings (see Table 2) or by manually setting the PPM count and divide ratio. To calibrate the VCO frequency, the DS125DF410 searches through the available VCO coarse tuning settings and counts the divided VCO frequency using the 25 MHz reference as a clock source. The VCO coarse tuning setting which provides the VCO frequency closest to the required frequency is stored, and this coarse tuning setting is used for subsequent operation. This produces a fast, robust phase lock to the input signal.