JAJSBK7H January   2012  – February 2018 DS125DF410


  1. 特長
  2. アプリケーション
  3. 概要
    1.     代表的なアプリケーションの図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 Signal Detect
      3. 7.3.3 CTLE
      4. 7.3.4 DFE
      5. 7.3.5 Clock and Data Recovery
      6. 7.3.6 Output Driver
      7. 7.3.7 Device Configuration
        1. Rate and Subrate Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 7.4.2 Address Lines <ADDR_[3:0]>
      3. 7.4.3 SDA and SDC
      4. 7.4.4 Standards-Based Modes
        1. Ref_mode 3 Mode (Reference Clock Required)
        2. False Lock Detector Setting
        3. Reference Clock In
        4. Reference Clock Out
        5. Driver Output Voltage
        6. Driver Output De-Emphasis
        7. Driver Output Rise/Fall Time
        8. INT
        9. LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    5. 7.5 Programming
      1. 7.5.1  SMBus Strap Observation
      2. 7.5.2  Device Revision and Device ID
      3. 7.5.3  Control/Shared Register Reset
      4. 7.5.4  Interrupt Channel Flag Bits
      5. 7.5.5  SMBus Master Mode Control Bits
      6. 7.5.6  Resetting Individual Channels of the Retimer
      7. 7.5.7  Interrupt Status
      8. 7.5.8  Overriding the CTLE Boost Setting
      9. 7.5.9  Overriding the VCO Search Values
      10. 7.5.10 Overriding the Output Multiplexer
      11. 7.5.11 Overriding the VCO Divider Selection
      12. 7.5.12 Using the PRBS Generator
      13. 7.5.13 Using the Internal Eye Opening Monitor
      14. 7.5.14 Overriding the DFE Tap Weights and Polarities
      15. 7.5.15 Enabling Slow Rise/Fall Time on the Output Driver
      16. 7.5.16 Inverting the Output Polarity
      17. 7.5.17 Overriding the Figure of Merit for Adaptation
      18. 7.5.18 Setting the Rate and Subrate for Lock Acquisition
      19. 7.5.19 Setting the Adaptation/Lock Mode
      20. 7.5.20 Initiating Adaptation
      21. 7.5.21 Setting the Reference Enable Mode
      22. 7.5.22 Overriding the CTLE Settings Used for CTLE Adaptation
      23. 7.5.23 Setting the Output Differential Voltage
      24. 7.5.24 Setting the Output De-Emphasis Setting
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
      2. 7.6.2 Bit Fields in the Register Set
      3. 7.6.3 Writing to and Reading from the Control/Shared Registers
      4. 7.6.4 Channel Select Register
      5. 7.6.5 Reading to and Writing from the Channel Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報



SMBus Master Mode and SMBus Slave Mode

In SMBus master mode the DS125DF410 reads its initial configuration from an external EEPROM upon power-up. A description of the operation of this mode appears in a separate application note.

Some of the pins of the DS125DF410 perform the same functions in SMBus master and SMBus slave mode. Once the DS125DF410 has finished reading its initial configuration from the external EEPROM in SMBus master mode it reverts to SMBus slave mode and can be further configured by an external controller over the SMBus. There are two pins that provide unique functions in SMBus master mode. These are as follows:


These pins are meant to work together. When the DS125DF410 is powered up in SMBus master mode, it reads its configuration from the external EEPROM when the READ_EN pin goes low. When the DS125DF410 is finished reading its configuration from the external EEPROM, it drives its ALL_DONE pin low. In applications where there is more than one DS125DF410 on the same SMBus, bus contention can result if more than one DS125DF410 tries to take command of the SMBus at the same time. The READ_EN and ALL_DONE pins prevent this bus contention.

The system should be designed so that the READ_EN pin of one of the DS125DF410s in the system is driven low on power-up. This DS125DF410 will take command of the SMBus on power-up and will read its initial configuration from the external EEPROM. When it is finished reading its configuration, it will set its ALL_DONE pin low. This pin should be connected to the READ_EN pin of another DS125DF410. When this DS125DF410 senses its READ_EN pin driven low, it will take command of the SMBus and read its initial configuration from the external EEPROM, after which it will set its ALL_DONE pin low. By connecting the ALL_DONE pin of each DS125DF410 to the READ_EN pin of the next DS125DF410, each DS125DF410 can read its initial configuration from the EEPROM without causing bus contention.

For SMBus slave mode, the READ_EN pin must be tied low. Do not leave it floating or tie it high.

A connection diagram showing several DS125DF410s along with an external EEPROM and an external SMBus master is shown in Figure 5 below. The SMBus master must be prevented from trying to take control of the SMBus until the DS125DF410s have finished reading their initial configurations from the EEPROM.

DS125DF410 30161008.gifFigure 5. Connection Diagram for Multiple DS125DF410s in SMBus Master Mode

In SMBus master mode after the DS125DF410 has finished reading its initial configuration from the external EEPROM it reverts to SMBus slave mode. In either mode the SMBus data and clock lines, SDA and SDC, are used. Also, in either mode, the SMBus address is latched in on the address strap lines on power-up. In SMBus slave mode, if the READ_EN pin is not tied low, the DS125DF410 will not latch in the address on its address strap lines. It will instead latch in an SMBus write address of 0x30 regardless of the state of the address strap lines. This is a test feature. Obviously a system with multiple retimers cannot operate properly if all the retimers are responding to the same SMBus address. Tie the READ_EN pin low when operating in SMBus slave mode to avoid this condition.

The DS125DF410 reads its SMBus address upon power-up from the SMBus address lines.