JAJSBK7H January 2012 – February 2018 DS125DF410
Register 0x04, bits 5 and 4 and register 0x05, bits 7 and 4
Register 0x04, bit 5, can be used to reset the SMBus master mode. This bit should not be set if the DS125DF410 is in SMBus slave mode. This is an undefined condition.
When this bit is set, if the EN_SMB pin is floating (meaning that the DS125DF410 is in SMBus master mode), then the DS125DF410 will read the contents of the external EEPROM when the READ_EN pin is pulled low. This bit is not self-clearing, so it should be cleared after it is set.
When the DS125DF410 EN_SMB pin is floating (meaning that the DS125DF410 is in SMBus master mode), it will read from its external EEPROM when its READ_EN pin goes low. After the EEPROM read operation is complete, register 0x05, bit 4 will be set. Alternatively, the DS125DF410 will read from its external EEPROM when triggered by register 0x04, bit 4, as described below.
When register 0x04, bit 4, is set, the DS125DF410 reads its configuration from an external EEPROM over the SMBus immediately. When this bit is set, the DS125DF410 does not wait until the READ_EN pin is pulled low to read from the EEPROM. This EEPROM read occurs whether the DS125DF410 is in SMBus master mode or not. If the read from the EEPROM is not successful, for example because there is no EEPROM present, then the DS125DF410 may hang up and a power-up reset may be necessary to return it to proper operation. You should only set this bit if you know that the EEPROM is present and properly configured.
If the EEPROM read has already completed, then setting register 0x04, bit 4, will not have any effect. To cause the DS125DF410 to read from the EEPROM again it is necessary to set bit 5 of register 0x04, resetting the SMBus master mode. If the DS125DF410 is not in SMBus master mode, do not set this bit. After setting this bit, it should be cleared before further SMBus operations.
After SMBus master mode has been reset, the EEPROM read may be initiated either by pulling the READ_EN pin low or by then setting register 0x04, bit 4.
Register 0x05, bit 7, disables SMBus master mode. This prevents the DS125DF410 from trying to take command of the SMBus to read from the external EEPROM. Obviously this bit will have no effect if the EEPROM read has already taken place. It also has no effect if an EEPROM read is currently in progress. The only situations in which disabling EEPROM master mode read is valid are (1) when the DS125DF410 is in SMBus master mode, but the READ_EN pin has not yet gone low, and (2) when register 0x04, bit 5, has been used to reset SMBus master mode but the EEPROM read operation has not yet occurred.
Do not set this bit and bit 4 of register 0x04 simultaneously. This is an undefined condition and can cause the DS125DF410 to hang up.