JAJSBK7H January   2012  – February 2018 DS125DF410


  1. 特長
  2. アプリケーション
  3. 概要
    1.     代表的なアプリケーションの図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 Signal Detect
      3. 7.3.3 CTLE
      4. 7.3.4 DFE
      5. 7.3.5 Clock and Data Recovery
      6. 7.3.6 Output Driver
      7. 7.3.7 Device Configuration
        1. Rate and Subrate Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 7.4.2 Address Lines <ADDR_[3:0]>
      3. 7.4.3 SDA and SDC
      4. 7.4.4 Standards-Based Modes
        1. Ref_mode 3 Mode (Reference Clock Required)
        2. False Lock Detector Setting
        3. Reference Clock In
        4. Reference Clock Out
        5. Driver Output Voltage
        6. Driver Output De-Emphasis
        7. Driver Output Rise/Fall Time
        8. INT
        9. LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    5. 7.5 Programming
      1. 7.5.1  SMBus Strap Observation
      2. 7.5.2  Device Revision and Device ID
      3. 7.5.3  Control/Shared Register Reset
      4. 7.5.4  Interrupt Channel Flag Bits
      5. 7.5.5  SMBus Master Mode Control Bits
      6. 7.5.6  Resetting Individual Channels of the Retimer
      7. 7.5.7  Interrupt Status
      8. 7.5.8  Overriding the CTLE Boost Setting
      9. 7.5.9  Overriding the VCO Search Values
      10. 7.5.10 Overriding the Output Multiplexer
      11. 7.5.11 Overriding the VCO Divider Selection
      12. 7.5.12 Using the PRBS Generator
      13. 7.5.13 Using the Internal Eye Opening Monitor
      14. 7.5.14 Overriding the DFE Tap Weights and Polarities
      15. 7.5.15 Enabling Slow Rise/Fall Time on the Output Driver
      16. 7.5.16 Inverting the Output Polarity
      17. 7.5.17 Overriding the Figure of Merit for Adaptation
      18. 7.5.18 Setting the Rate and Subrate for Lock Acquisition
      19. 7.5.19 Setting the Adaptation/Lock Mode
      20. 7.5.20 Initiating Adaptation
      21. 7.5.21 Setting the Reference Enable Mode
      22. 7.5.22 Overriding the CTLE Settings Used for CTLE Adaptation
      23. 7.5.23 Setting the Output Differential Voltage
      24. 7.5.24 Setting the Output De-Emphasis Setting
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
      2. 7.6.2 Bit Fields in the Register Set
      3. 7.6.3 Writing to and Reading from the Control/Shared Registers
      4. 7.6.4 Channel Select Register
      5. 7.6.5 Reading to and Writing from the Channel Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報



Overriding the Output Multiplexer

Register 0x09, bit 5, Register 0x14, bits 7:6, and Register 0x1e, bits 7:5

By default, the DS125DF410 output for each channel will be as shown in Table 5.

Table 5. Default Output Status Description

Not Present No Signal Detected Muted
Present Not Locked Muted
Present Locked Retimed Data

This default behavior can be modified by register writes.

Register 0x1e, bits 7:5, contain the output multiplexer override value. The values of this three-bit field and the corresponding meanings of each are shown in Table 6.

Table 6. Output Multiplexer Override Settings

0x7 Mute Default when no signal is present or when the retimer is unlocked
0x6 N/A Invalid Setting
0x5 10 MHz Clock Internal 10 MHz clock
Clock frequency may not be precise, There is no production test coverage for this and is only use for testing.
0x4 PRBS Generator PRBS Generator must be enabled to output PRBS sequence
0x3 VCO Q-Clock Register 0x09, bit 4, and register 0x1e, bit 0, must be set to enable the VCO Q-Clock. There is no production test coverage for this and is only use for testing.
0x2 VCO I-Clock There is no production test coverage for this and is only use for testing.
0x1 Retimed Data Default when the retimer is locked
0x0 Raw Data Bypass the CDR, output is not retimed and must set bit 5 of register 0x09 and bit 7 of 0x3F.

If the output multiplexer is not overridden, that is, if bit 5 of register 0x09 is not set, then the value in register 0x1e, bits 7:5, controls the output produced when the retimer has a signal at its input, but is not locked to it. The default value for this bit field, 0x7, causes the retimer output to mute when the retimer is not locked to an input signal. Writing a value of 0x0 to this bit field, for example, will cause the retimer to output raw data (not retimed) when it is not locked to its input signal.

Set the override bit to 1, bit 5 of register 0x09, will cause the retimer to output the value selected by the bit field in register 0x1e, bits 7:5. In the raw data mode (CDR is bypassed), the register 0x3F, bit 7 should be set to 1, this will disable the fast cap re-search which stops the output from powering down (muting) during raw mode.

When no signal is present at the input to the selected channel of the DS125DF410 the signal detect circuitry will power down the channel. This includes the output driver which is therefore muted when no signal is present at the input. If you want to get an output when no signal is present at the input, for example to enable a free-running PRBS sequence, the first step is to override the signal detect. In order to force the signal detect on, set bit 7 and clear bit 6 of channel register 0x14. Even if there is no signal at the input to the channel, the channel will be enabled. If the channel was disabled before, the current drain from the supply will increase by 100–150 mA depending upon the other channel settings in the device. This increased current drain indicates that the channel is now enabled.

The second step is to override the output multiplexer setting. This is accomplished by setting bit 5 of register 0x09, the output multiplexer override. Once this bit is set, the value of register 0x1e, bits 7:5 will control the output of the channel. Note that if either retimed or raw data is selected, the output will just be noise. The device output may saturate to a static 1 or 0.

If there is no signal, the VCO clock will be free-running. Its frequency will depend upon the divider and CAP DAC settings and it will vary from part to part and over temperature.

If the PRBS generator is enabled, the PRBS generator output can be selected. This can either be at a data rate determined by the free-running VCO or at a data rate determined by the input signal, if one is present. If a signal is present at the input and the DS125DF410 can lock to it, the output of the PRBS generator will be synchronous with the input signal, but the bit stream output will be determined by the PRBS generator selection.

The 10 MHz clock is always available at the output when the output multiplexer is overridden. The 10 MHz clock is a free-running oscillator in the DS125DF410 and is not synchronous to the input or to anything else in the system. The clock frequency will be approximately 10 MHz, but this will vary from part to part.

If there is a signal present at the input, it is not necessary to override the signal detect. Clearing bits 7 and 6 of register 0x14 will return control of the signal detect to the DS125DF410. Normally, when the retimer is locked to a signal at its input, it will output retimed data. However, if desired, the output multiplexer can be overridden in this condition to output raw data. It can also be set to output any of the other signals shown in Table 6. If there is an input signal, and if the DS125DF410 is locked to it, the VCO I-Clock, the VCO Q-Clock, and the output of the PRBS generator, if it is enabled, will be synchronous to the input signal.

When a signal is present at the input, it might be desired to output the raw data in order to see the effects of the CTLE and (for the DS125DF410) the DFE without the CDR. It might also be desired to enable the PRBS generator and output this signal, replacing the data content of the input signal with the internally-generated PRBS sequence.