JAJSBK7H January 2012 – February 2018 DS125DF410
Register 0x08, bits 4:0, Register 0x09, bit 7, Register 0x0b, bits 4:0, Register 0x36, bits 5:4 and 2:0, and Register 0x2f, bits 7:6 and 5:4
Registers 0x08 and 0x0b contain CAP DAC override values. Normally, when bits 5:4 of register 0x36 are set to 2'b11, then the DS125DF410 performs an initial search to determine the correct CAP DAC setting (coarse VCO tuning) for the selected rate and subrate. The rate and subrate settings (bits 7:6 and 5:4 of register 0x2f) determine the frequency range to be searched, with the 25 MHz reference clock used as the frequency reference for the frequency search.
The CAP DAC value can be overridden by writing new values to bits 4:0 of register 0x08 (for CAP DAC setting 1) and bits 4:0 of 0x0b (for CAP DAC setting 2). The override bit, bit 7 of register 0x09 must be set for the override CAP DAC values to take effect. Since the valid rate and subrate setting for 10 GbE and 1 GbE applies to multiple data rates, there are two CAP DAC values for this rate. The first is in register 0x08, bits 4:0, and the second is in register 0x0b, bits 4:0. The DS125DF410 will use the CAP DAC value in register 0x08 for the larger divide ratio (8) associated with the selected rate and subrate to try and acquire lock. If it fails to acquire lock, it will use the CAP DAC value in register 0x0b with the smaller divide ratio (higher VCO frequency) associated with the selected rate and subrate (1). It will continue to try to acquire lock in this way until it either succeeds or the override bit (bit 7 of register 0x09) is cleared.