JAJSBK7H January 2012 – February 2018 DS125DF410
Register 0x36, bits 5:4
The reference clock mode is set by a two-bit field, register 0x36, bits 5:4. This field should always be set to a value of 3 or 2'b11.
A 25 MHz reference clock signal must be provided on the reference in pin (pin 19). The use of the reference clock in the DS125DF410 is explained below.
First, the reference clock allows the DS125DF410 to calibrate its VCO frequency at power-up and upon reset. This enables the DS125DF410 to determine the optimum coarse VCO tuning setting a-priori, which makes phase lock much faster. The DS125DF410 is not required to tune through the available coarse VCO tuning settings as it tries to acquire lock to an input signal. It can select the correct setting immediately.
Second, if the DS125DF410 loses lock for some reason and the VCO drifts from its phase-locked frequency, the DS125DF410 can detect this very quickly using the reference clock. Detecting an out-of-lock condition quickly allows the DS125DF410 to raise an interrupt indicating that it has lost lock quickly, which the system controller can then service to correct the problem quickly.
Finally, some data signals with large jitter spurs in their frequency spectra can cause the DS125DF410 to false lock. This occurs when the data pattern exhibits strong discrete frequency components in its frequency spectrum, or when the data pattern has a lot of periodic jitter imposed on it. If you look at such a signal in the frequency domain using a spectrum analyzer, it will clearly show “spurs” close in to the fundamental data rate frequency. These spurs can cause the DS125DF410 to false lock.
Using the 25 MHz reference clock, the DS125DF410 can detect when it is locked to a jitter spur. When this happens, the DS125DF410 will re-initiate the adaptation and lock sequence until it locks to the correct data rate. This provides immunity to false lock conditions.