JAJSBK7H January   2012  – February 2018 DS125DF410


  1. 特長
  2. アプリケーション
  3. 概要
    1.     代表的なアプリケーションの図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 Signal Detect
      3. 7.3.3 CTLE
      4. 7.3.4 DFE
      5. 7.3.5 Clock and Data Recovery
      6. 7.3.6 Output Driver
      7. 7.3.7 Device Configuration
        1. Rate and Subrate Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 7.4.2 Address Lines <ADDR_[3:0]>
      3. 7.4.3 SDA and SDC
      4. 7.4.4 Standards-Based Modes
        1. Ref_mode 3 Mode (Reference Clock Required)
        2. False Lock Detector Setting
        3. Reference Clock In
        4. Reference Clock Out
        5. Driver Output Voltage
        6. Driver Output De-Emphasis
        7. Driver Output Rise/Fall Time
        8. INT
        9. LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    5. 7.5 Programming
      1. 7.5.1  SMBus Strap Observation
      2. 7.5.2  Device Revision and Device ID
      3. 7.5.3  Control/Shared Register Reset
      4. 7.5.4  Interrupt Channel Flag Bits
      5. 7.5.5  SMBus Master Mode Control Bits
      6. 7.5.6  Resetting Individual Channels of the Retimer
      7. 7.5.7  Interrupt Status
      8. 7.5.8  Overriding the CTLE Boost Setting
      9. 7.5.9  Overriding the VCO Search Values
      10. 7.5.10 Overriding the Output Multiplexer
      11. 7.5.11 Overriding the VCO Divider Selection
      12. 7.5.12 Using the PRBS Generator
      13. 7.5.13 Using the Internal Eye Opening Monitor
      14. 7.5.14 Overriding the DFE Tap Weights and Polarities
      15. 7.5.15 Enabling Slow Rise/Fall Time on the Output Driver
      16. 7.5.16 Inverting the Output Polarity
      17. 7.5.17 Overriding the Figure of Merit for Adaptation
      18. 7.5.18 Setting the Rate and Subrate for Lock Acquisition
      19. 7.5.19 Setting the Adaptation/Lock Mode
      20. 7.5.20 Initiating Adaptation
      21. 7.5.21 Setting the Reference Enable Mode
      22. 7.5.22 Overriding the CTLE Settings Used for CTLE Adaptation
      23. 7.5.23 Setting the Output Differential Voltage
      24. 7.5.24 Setting the Output De-Emphasis Setting
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
      2. 7.6.2 Bit Fields in the Register Set
      3. 7.6.3 Writing to and Reading from the Control/Shared Registers
      4. 7.6.4 Channel Select Register
      5. 7.6.5 Reading to and Writing from the Channel Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報



Standards-Based Modes

The DS125DF410 is designed to automatically operate with various multi-band data standards.

The first set of register writes constrain the coarse VCO tuning and the VCO divider ratios. When these registers are set as indicated in Table 2, the DS125DF410 restricts its coarse VCO tuning to a set of coarse tuning values. It also restricts the VCO divider ratio to the set of divider ratios required to cover the frequency bands for the desired data rate standard. This enables the DS125DF410 to acquire phase lock more quickly than would be possible if the coarse tuning range were unrestricted.

Table 2. Standards-Based Modes Register Settings

VALUE (hex)
InfiniBand 2.5, 5, 10 10.0 1, 2, 4 0x26
CPRI1 2.4576, 4.9152, 9.8304 9.8304 1, 2, 4 0x36
CPRI2 3.072, 6.144 12.288 2, 4 0x46
PROP3 6.25 12.5 2 0xA6
Interlaken1 3.125, 6.25 12.5 2, 4 0xB6
Interlaken2 10.3125 10.3125 1 0xC6
Ethernet 1.25, 10.3125 10.0, 10.3125 1, 8 0xF6

As an example of the usage of the registers in Table 2, assume that the retimer is required to operate in 10 GbE or 1GbE mode. By setting register 0x2f, bits 7:4, to 4'b1111, the DS125DF410 will automatically set its divider ratio and its coarse VCO tuning setting to lock to either a 10 GbE signal (at 10.3125 Gb/s) or a 1 GbE signal (at 1.25 Gb/s) at its input.

For some standards shown in the table above, the required VCO frequency is the same for each data rate in the standard. Only the divider ratios are different. The retimer can automatically switch between the required divider ratios with a single set of register settings.

For other data rates, it is also necessary to set the expected PPM count and the PPM count tolerance. These are the values the retimer uses to detect a valid frequency lock.

For the 10 GbE and 1 GbE mode shown in the table above, two frequency groups are defined. These two frequency groups are referred to as “Group 0”, for 1 GbE, and “Group 1”, for 10 GbE. This same frequency group structure is present for all frequency modes, but for some modes the expected frequency for both groups is the same. The expected PPM count information for Group 0 is set in registers 0x60 and 0x61. For Group 1, it is set in registers 0x62 and 0x63. For both groups, the PPM count tolerance is set in register 0x64.

The value of the PPM count for either group is computed the same way from the expected data rate in Gbps, RGbps. The PPM count value, denoted NPPM, is computed by NPPM = RGbps × 1280.

As an example we consider the PPM count setup for 10 GbE and 1 GbE. The expected PPM count for Group 0, which in this case is 1 GbE, is set in registers 0x60 and 0x61. The expected VCO frequency for 1 G is 10.0 G. The actual data rate for 1 GbE, which is 8B/10B coded, is 1.25 Gbps. With a VCO divide ratio of 8, which is the divide ratio automatically used by the retimer for 1 GbE, this yields a VCO frequency of 10.0 GHz.

We compute the PPM count as NPPM = 10.0 × 1280 = 12800. This is a decimal value. In hexadecimal, this is 0x3200.

The lower-order byte is loaded into register 0x60. The higher order byte, 0x32, is loaded into the 7 least significant bits of register 0x61. In addition, bit 7 of register 0x61 is set, indicating manual load of the PPM count.

When this is complete, register 0x60 will contain 0x00. Register 0x61 will contain 0xb2.

For the example we are considering, Group 1 is for 10 GbE. Here the actual data rate for the 64/66B encoded 10 GbE data is 10.3125 Gbps. For 10 GbE, the retimer automatically uses a divide ratio of 1, so the VCO frequency is also 10.3125 GHz. For 10 GbE, we compute the expected PPM count as NPPM = 10.3125 × 1280 = 13200. Again, this is a decimal value. In hexadecimal, this is 0x3390.

The lower order byte for Group 1, 0x90, is loaded into register 0x62. The higher-order byte, 0x33, is loaded into the 7 least-significant bits of register 0x63. As with the Group 0 settings, bit 7 of register 0x63 is also set.

When this is complete, register 0x62 will contain 0x90. Register 0x63 will contain 0xb3.

Finally, register 0x64 should be set to a value of 0xff. This is the PPM count tolerance. The resulting tolerance in parts per million is given by TolPPM = (1 × 10-6 × NTOL) / NPPM. In this equation, NTOL is the 4-bit tolerance value loaded into the upper or lower four bits of register 0x64. For the example we are using here, both of these values are 0xf, or decimal 15. For a PPM count value of 12800, for Group 0, this yields a tolerance of 1172 parts per million. For a PPM count value of 13200, for Group 1, this yields a tolerance of 1136 parts per million.

These tolerance values can be reduced if it is known that the frequency accuracy of the system and of the 25 MHz reference clock are very good. For most applications, however, a value of 0xff in register 0x64 will give robust performance.

For all the other standards shown in Table 2 the expected PPM count for Group 0 (registers 0x60 and 0x61) and Group 1 (registers 0x62 and 0x63) will be set the same, since there is only one VCO frequency for these standards. The expected PPM count and tolerance are computed as described above for 10 GbE and 1 GbE. The same values are written to each pair of PPM count registers for these standards.

As is the case with the standards-based mode of operation, the expected PPM count value and the PPM count tolerance must be written to registers 0x60, 0x61, 0x62, 0x63, and 0x64. These are computed exactly as described above for the standards-based mode of operation. Since the frequency-range-based mode of operation uses both Group 0 and Group 1 with the same expected PPM count, the same values should be loaded into the pairs of registers 0x60 and 0x62, and 0x61 and 0x63.

As an example, suppose that the expected data rate is 8.5 Gbps. The VCO frequency for the frequency-range based mode of operation is also 8.5 GHz. So we compute NPPM = 8.5 × 1280 = 10880. This is a decimal value. In hexadecimal this is 0x2a80.

We write the lower-order byte, 0x80 into registers 0x60 and 0x62. We write the higher order byte, 0x2a, into the least-significant 7 bits of registers 0x61 and 0x63. We also set bit 7 of registers 0x61 and 0x63. When this operation is complete, registers 0x60 and 0x62 will contain a value of 0x80. Registers 0x61 and 0x63 will contain a value of 0xaa.

We also write the PPM tolerance into both the upper and lower four bits of register 0x64. If we write this register to a value of 0xff, then the PPM count tolerance in parts per million will be given by TolPPM = (1 × 10-6 × NTOL) / NPPM = 1379 parts per million. This value will be appropriate for most systems.

In summary, for data rates that correspond to the pre-defined standards for the DS125DF410, the standards-based mode of operation can be used. This mode offers automatic switching of the divide ratio (and, for 10 GbE and 1 GbE, the VCO frequency) to easily accommodate operation over harmonically-related data rates. For data rates that are not covered by the pre-defined standards, the frequency-range-based mode of operation can be used. This mode works with a fixed divider ratio, which is nominally 1. However, the divider ratio can be forced to other values if desired.

The register configuration procedure is as follow:

  1. Select the desired channel of the DS125DF410 by writing the appropriate value to register 0xff.
  2. Set bits 5:4 of register 0x36 to a value of 2'b11 as described above to enable the 25 MHz reference clock.
  3. Write registers 0x2f with the correct values.
  4. Compute the expected PPM count values for Group 0 and Group 1 as described above.
  5. Write the expected PPM count values into registers 0x60-0x63 as described above, setting bit 7 of both registers 0x61 and 0x63.
  6. Set the value 0xff into register 0x64 for an approximate PPM count tolerance of 1100-1400 PPM.
  7. Reset the retimer CDR by setting and then clearing bits 3:2 of register 0x0a.

If there is a signal at the correct data rate present at the input to the DS125DF410, the retimer will lock to it.

In ref_mode 3, bits 5:4 of register 0x36 are set to 2'b11, it is not necessary to set the CAP DAC values the DS125DF410 determines the correct CAP DAC values automatically.

Because it is not necessary to set the CAP DAC values for Group 0 and Group 1 a-priori in ref_mode 3, the DS125DF410 can be set up to use automatically switching divider ratios and arbitrary VCO frequencies in this mode. The mapping of values in register 0x2f, bits 7:4, versus the divider ratios used for each of the two groups is shown in Table 3.

Table 3. Divider Ratio Settings versus Register 0x2f Setting

0x2f, Bits 7:4
4'b0010 1, 2, 4 1, 2, 4
4'b0011 1, 2, 4 1, 2, 4
4'b0100 2, 4 2, 4
4'b0110 1, 2, 4, 8 1, 2, 4, 8
4'b1010 2 2
4'b1011 2, 4 2, 4
4'b1100 1 1
4'b1111 8 1

Note that for the entries in Table 3 where the divider ratios are the same for the two groups, the expected PPM count for the two groups does not have to be the same. Therefore, in ref_mode 3, a single set of register settings can be used to specify multiple VCO frequencies either with the same divider ratio or with different divider ratios.