JAJU732C June   2019  – July 2022

 

  1.   概要
  2.   Resources
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21530
      2. 2.2.2  AMC1311
      3. 2.2.3  AMC3302
      4. 2.2.4  AMC3306M05
      5. 2.2.5  LM76003
      6. 2.2.6  LMZ31707
      7. 2.2.7  OPA320
      8. 2.2.8  ISO7721
      9. 2.2.9  SN6501
      10. 2.2.10 SN6505B
      11. 2.2.11 TMP235
      12. 2.2.12 LMT87
      13. 2.2.13 TL431
      14. 2.2.14 LMV762
      15. 2.2.15 TMS320F280049 C2000 MCU
      16. 2.2.16 TMDSCNCD280049C
    3. 2.3 System Design Theory
      1. 2.3.1 Dual Active Bridge Analogy With Power Systems
      2. 2.3.2 Dual-Active Bridge - Switching Sequence
      3. 2.3.3 Dual-Active Bridge - Zero Voltage Switching (ZVS)
      4. 2.3.4 Dual-Active Bridge - Design Considerations
        1. 2.3.4.1 Leakage Inductor
        2. 2.3.4.2 Effect of Inductance on Current
        3. 2.3.4.3 Phase Shift
        4. 2.3.4.4 Capacitor Selection
        5. 2.3.4.5 Soft Switching Range
        6. 2.3.4.6 Switching Frequency
        7. 2.3.4.7 Transformer Selection
        8. 2.3.4.8 SiC MOSFET Selection
      5. 2.3.5 Loss Analysis
        1. 2.3.5.1 Design Equations
        2. 2.3.5.2 SiC MOSFET and Diode Losses
        3. 2.3.5.3 Transformer Losses
        4. 2.3.5.4 Inductor Losses
        5. 2.3.5.5 Gate Driver Losses
        6. 2.3.5.6 Efficiency
        7. 2.3.5.7 Thermal Considerations
  8. 3Circuit Description
    1. 3.1 Power Stage
    2. 3.2 DC Voltage Sensing
      1. 3.2.1 Primary DC Voltage Sensing
      2. 3.2.2 Secondary DC Voltage Sensing
    3. 3.3 Current Sensing
    4. 3.4 Power Architecture
      1. 3.4.1 Auxiliary Power Supply
      2. 3.4.2 Isolated Power Supply for Sense Circuits
    5. 3.5 Gate Driver
      1. 3.5.1 Gate Driver Circuit
      2. 3.5.2 Gate Driver Bias Power Supply
      3. 3.5.3 Gate Driver Discrete Circuits - Short-Circuit Detection and Two Level Turn Off
  9. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Required Hardware and Software
      1. 4.1.1 Hardware
      2. 4.1.2 Software
        1. 4.1.2.1 Getting Started With Software
        2. 4.1.2.2 Pin Configuration
        3. 4.1.2.3 PWM Configuration
        4. 4.1.2.4 High-Resolution Phase Shift Configuration
        5. 4.1.2.5 ADC Configuration
        6. 4.1.2.6 ISR Structure
    2. 4.2 Test Setup
    3. 4.3 PowerSUITE GUI
    4. 4.4 LABs
      1. 4.4.1 Lab 1
      2. 4.4.2 Lab 2
      3. 4.4.3 Lab 3
      4. 4.4.4 Lab 4
      5. 4.4.5 Lab 5
    5. 4.5 Test Results
      1. 4.5.1 Open-Loop Performance
      2. 4.5.2 Closed-Loop Performance
  10. 5Design Files
    1. 5.1 Schematics
    2. 5.2 Bill of Materials
    3. 5.3 PCB Layout Recommendations
      1. 5.3.1 Layout Prints
    4. 5.4 Altium Project
    5. 5.5 Gerber Files
    6. 5.6 Assembly Drawings
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7Terminology
  13. 8About the Author
  14. 9Revision History

Open-Loop Performance

Table 4-4 shows the system efficiency as a function of output power. The converter output power was varied by changing the load and the phase angle between the input and output bridge to reach 10 kW. The table shows that the converter achieves a peak efficiency of 98.2% at approximately 6 kW and has a full load efficiency of 97.6% at 10 kW. Figure 4-45 shows the measured efficiency of the converter at different power levels.

Table 4-4 Converter Efficiency Results
TESTING CONDITIONS INPUT VOLTAGE VIN: 800 V, Switching frequency: 100 kHz, Phase shift: Between 10° to 15°, Load resistance: Decreased from 128 Ω to 34 Ω INPUT VOLTAGE VIN: 800 V, Switching frequency: 100 kHz, Load resistance: 26 Ω, Phase shift: Increased from 16° to 23°
Load in Watts 500 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Efficiency 91% 94% 97.50% 97.70% 97.90% 98% 98.16% 97.90% 97.80% 97.75% 97.60%
GUID-72735699-52E8-4149-B33B-DBDD68B4F4B3-low.gifFigure 4-45 Efficiency Versus Output Power

Table 4-5 shows the resistive loads that were used to vary the output power from light load to full load. The input voltage is kept constant at 800 V. As seen from the table, to achieve power transfer of 10 kW, the phase angle is varied by keeping the load resistance fixed at 26 Ω. For a particular power output, input voltage, output voltage, switching frequency, turns ratio, and leakage inductance, the phase angle is calculated using Equation 14.

Table 4-5 Results Summary
INPUT CURRENT (A) INPUT POWER (W) OUTPUT CURRENT (A) OUTPUT VOLTAGE (V) OUTPUT POWER (W) EFFICIENCY LOAD RESISTANCE (Ω) OBSERVED PHASE SHIFT (deg) ACTUAL CALCULATED PHASE SHIFT (deg)
2.47 1976 3.875 496 1922 97.3% 128 10 7
4.37 3496 7.07 483.4 3416 97.7% 68 10 7
5.51 4408 9.06 473 4286 97.2% 52 10 8.5
7.79 6232 13.42 455.6 6114 98.1% 34 15 13
8.86 7088 16.49 419.4 6916 97.6% 26 16.2 16.32
11.56 9248 18.85 479.4 9036 97.7% 26 21.6 18.9
12.62 10096 19.68 500.5 9855 97.6% 26 23 20

Table 4-5 shows that the observed phase shift (calculated from the PWM settings) and the actual phase shift calculated from formula varies slightly. The theoretical formula gives a good starting point to set the phase shift, but depending on the load applied to the converter, there is a requirement for fine adjustment of phase to deliver the required power. At a phase shift of 23 degrees, full power transfer of 10 kW and an output voltage of 500 V for an input voltage of 800 V at a switching frequency of 100 kHz are obtained. The closed-loop regulation of output voltage to the desired value by controlling phase is being implemented and will be available following the release of this design.

Figure 4-46 shows the drain voltage (dark blue), gate voltage (cyan), and inductor current (purple) waveforms of the primary side SiC MOSFET at a 10-kW power level. The drain voltage switches between zero and 800 V, the gate voltage waveform switches from +15 / –4 V, and the inductor current has a trapezoidal signature with peak current of approximately 20 A.

GUID-AEF415DE-D711-4E3F-A5C4-A298FCC9603F-low.pngFigure 4-46 Waveforms at 10 kW

Figure 4-47 shows the waveforms at the instant of turn on. Gating pulses (dark blue) are applied to turn on the MOSFET once the drain voltage (cyan) falls to zero. This results in ZVS turn on of the MOSFET. Figure 4-48 shows the switch turn off waveform. The turn off process results in switching losses. This can be minimized by placing output capacitors across MOSFETs.

GUID-70E6AFD3-E5C3-4F9F-8B82-86BF154EA60C-low.pngFigure 4-47 Switch Turn on Waveforms
GUID-E81AF227-A264-44D2-9C6C-5B60F37640AB-low.pngFigure 4-48 Switch Turn Off Waveforms

Table 4-6 shows the dimensions of the converter. The calculated total power density of the converter is 2.32 kW/L, which is more than our targeted specification of 1 kW/L.

Table 4-6 Board Dimensions
AXISDIMENSIONS
X328 mm
Y160 mm
Z82 mm
Volume4.3 liter