JAJU732C June   2019  – July 2022

 

  1.   概要
  2.   Resources
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21530
      2. 2.2.2  AMC1311
      3. 2.2.3  AMC3302
      4. 2.2.4  AMC3306M05
      5. 2.2.5  LM76003
      6. 2.2.6  LMZ31707
      7. 2.2.7  OPA320
      8. 2.2.8  ISO7721
      9. 2.2.9  SN6501
      10. 2.2.10 SN6505B
      11. 2.2.11 TMP235
      12. 2.2.12 LMT87
      13. 2.2.13 TL431
      14. 2.2.14 LMV762
      15. 2.2.15 TMS320F280049 C2000 MCU
      16. 2.2.16 TMDSCNCD280049C
    3. 2.3 System Design Theory
      1. 2.3.1 Dual Active Bridge Analogy With Power Systems
      2. 2.3.2 Dual-Active Bridge - Switching Sequence
      3. 2.3.3 Dual-Active Bridge - Zero Voltage Switching (ZVS)
      4. 2.3.4 Dual-Active Bridge - Design Considerations
        1. 2.3.4.1 Leakage Inductor
        2. 2.3.4.2 Effect of Inductance on Current
        3. 2.3.4.3 Phase Shift
        4. 2.3.4.4 Capacitor Selection
        5. 2.3.4.5 Soft Switching Range
        6. 2.3.4.6 Switching Frequency
        7. 2.3.4.7 Transformer Selection
        8. 2.3.4.8 SiC MOSFET Selection
      5. 2.3.5 Loss Analysis
        1. 2.3.5.1 Design Equations
        2. 2.3.5.2 SiC MOSFET and Diode Losses
        3. 2.3.5.3 Transformer Losses
        4. 2.3.5.4 Inductor Losses
        5. 2.3.5.5 Gate Driver Losses
        6. 2.3.5.6 Efficiency
        7. 2.3.5.7 Thermal Considerations
  8. 3Circuit Description
    1. 3.1 Power Stage
    2. 3.2 DC Voltage Sensing
      1. 3.2.1 Primary DC Voltage Sensing
      2. 3.2.2 Secondary DC Voltage Sensing
    3. 3.3 Current Sensing
    4. 3.4 Power Architecture
      1. 3.4.1 Auxiliary Power Supply
      2. 3.4.2 Isolated Power Supply for Sense Circuits
    5. 3.5 Gate Driver
      1. 3.5.1 Gate Driver Circuit
      2. 3.5.2 Gate Driver Bias Power Supply
      3. 3.5.3 Gate Driver Discrete Circuits - Short-Circuit Detection and Two Level Turn Off
  9. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Required Hardware and Software
      1. 4.1.1 Hardware
      2. 4.1.2 Software
        1. 4.1.2.1 Getting Started With Software
        2. 4.1.2.2 Pin Configuration
        3. 4.1.2.3 PWM Configuration
        4. 4.1.2.4 High-Resolution Phase Shift Configuration
        5. 4.1.2.5 ADC Configuration
        6. 4.1.2.6 ISR Structure
    2. 4.2 Test Setup
    3. 4.3 PowerSUITE GUI
    4. 4.4 LABs
      1. 4.4.1 Lab 1
      2. 4.4.2 Lab 2
      3. 4.4.3 Lab 3
      4. 4.4.4 Lab 4
      5. 4.4.5 Lab 5
    5. 4.5 Test Results
      1. 4.5.1 Open-Loop Performance
      2. 4.5.2 Closed-Loop Performance
  10. 5Design Files
    1. 5.1 Schematics
    2. 5.2 Bill of Materials
    3. 5.3 PCB Layout Recommendations
      1. 5.3.1 Layout Prints
    4. 5.4 Altium Project
    5. 5.5 Gerber Files
    6. 5.6 Assembly Drawings
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7Terminology
  13. 8About the Author
  14. 9Revision History

4.4.3 Lab 3

In the lab 3 build, the board is excited in secondary voltage close-loop ( DAB_vSecSensed_Volts).

This lab runs the voltage mode compensator, obtain open-loop transfer function of plant from SFRA, and design compensator for the plant in compensator design tool.

Launch the compensation designer which prompts to select a valid SFRA data file. Import the SFRA data from the run in lab 2 into the compensation designer to design a 2P2Zcompensator. Keep more margins during this iteration of the design to ensure that when the loop is closed, the system is stable. The following coefficient values are hard-coded in the SW. The compensation designer GUI gives information about the stability of the loop, gain margin, phase margin, and bandwidth of the loop. The coefficients can be modified in the compensation designer GUI.

#define DAB_GV_2P2Z_A1 ((float32_t) -1.8756666)
#define DAB_GV_2P2Z_A2 (float32_t) 0.8756666
#define DAB_GV_2P2Z_B0 (float32_t) 3.0092688
#define DAB_GV_2P2Z_B1 ((float32_t) -5.8788593)
#define DAB_GV_2P2Z_B2 (float32_t) 2.8696427
  • Test Setup for Lab 3 (Closed Voltage Loop - Vsec)

    Compile the project by selecting Lab 3: Closed Loop Voltage with Resistive Load in the drop-down menu of Project Options from PowerSUITE GUI. Ensure current and voltage limits are set per operating conditions.

    #if DAB_LAB == 3
#define DAB_CONTROL_RUNNING_ON C28X_CORE
#define DAB_POWER_FLOW DAB_POWER_FLOW_PRIM_SEC
#define DAB_INCR_BUILD DAB_CLOSED_LOOP_BUILD
#define DAB_TEST_SETUP DAB_TEST_SETUP_RES_LOAD
#define DAB_PROTECTION DAB_PROTECTION_ENABLED
#define DAB_CONTROL_MODE DAB_VOLTAGE_MODE
#define DAB_SFRA_TYPE 2
#define DAB_SFRA_AMPLITUDE (float32_t)DAB_SFRA_INJECTION_AMPLITUDE_LEVEL2
#endif

    Use the following steps to run voltage close loop:

    1. Run the project by clicking green run button in CCS
    2. Populate the required variables in the watch window by loading javascript ' setupdebugenv_lab3.js' in the scripting console
      GUID-20210818-SS0I-FCL1-45G6-XLHXHDHH5BKV-low.png Figure 4-34 Lab 3 Watch View Configuration
    3. Enable PWM by writing “1” to the DAB_clearTrip variable
    4. In the watch view, check if the DAB_vPrimSensed_Volts, DAB_iPrimSensed_Amps, DAB_vSecSensed_Volts, and DAB_iSecSensed_Amps variables are updating periodically
      GUID-20210818-SS0I-TJ8Q-ZBPM-RVZ5Z0XZ5JWC-low.png Figure 4-35 Lab 3 Watch View - Enable Closed Loop
    5. Set the output voltage by writing to DAB_vSecRef_Volts (in this example 200Vdc)
    6. Enable closed loop operation by writing “1” to the DAB_closeGvLoop variable. The controller automatically adjusts the phase shift from default 0.032 to 0.04178, depending upon the operating conditions to generate secondary output voltage to match with that of DAB_vSecRef_Volts.
      Note: In the software the maximum phase shift is limited to 0.065 as a safety precaution. Adjust the primary voltage to stay within the phase shift limits and still generate the required secondary voltage. Alternatively, the maximum allowed phase shift can be modified to 0.15 in the code.
    7. Slowly increase the input VPRIM DC voltage and adjust DAB_vSecRef_Volts accordingly to reach to the required operating point
    8. Test the closed-loop operation by varying DAB_vSecRef_Volts from 400 V to 500 V. Observe that the DAB_vSecSensed_Volts tracks this command reference.
  • Frequency response of closed loop voltage
    1. Run the SFRA by clicking on the SFRA icon. The SFRA GUI opens.
    2. Select the options for the device on the SFRA GUI; for example, for F280049, select floating point. Click the Setup Connection button. In the pop-up window, uncheck the boot-on-connect option and select an appropriate COM port. Select the OK button. Return to the SFRA GUI and click the Connect button.
    3. The SFRA GUI connects to the device. An SFRA sweep can now be started by clicking the Start Sweep button. The complete SFRA sweep takes a few minutes to finish. Monitor the activity in the progress bar on the SFRA GUI or by checking the flashing blue LED on the back of the control card, which indicates UART activity.

      The bode plot in Figure 4-36 is captured using a DF22 compensator.

      GUID-20210818-SS0I-DDSC-FDXV-LQ0ZGR5VN4KW-low.png
      Test condition: VIN = 600 V, IIN = 4.78 A, VOUT = 425 V, SFRA Amplitude = 0.002
      Figure 4-36 Lab 3 SFRA Open Loop Plot for the Closed Voltage Loop