JAJU732C June   2019  – July 2022

 

  1.   概要
  2.   Resources
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21530
      2. 2.2.2  AMC1311
      3. 2.2.3  AMC3302
      4. 2.2.4  AMC3306M05
      5. 2.2.5  LM76003
      6. 2.2.6  LMZ31707
      7. 2.2.7  OPA320
      8. 2.2.8  ISO7721
      9. 2.2.9  SN6501
      10. 2.2.10 SN6505B
      11. 2.2.11 TMP235
      12. 2.2.12 LMT87
      13. 2.2.13 TL431
      14. 2.2.14 LMV762
      15. 2.2.15 TMS320F280049 C2000 MCU
      16. 2.2.16 TMDSCNCD280049C
    3. 2.3 System Design Theory
      1. 2.3.1 Dual Active Bridge Analogy With Power Systems
      2. 2.3.2 Dual-Active Bridge - Switching Sequence
      3. 2.3.3 Dual-Active Bridge - Zero Voltage Switching (ZVS)
      4. 2.3.4 Dual-Active Bridge - Design Considerations
        1. 2.3.4.1 Leakage Inductor
        2. 2.3.4.2 Effect of Inductance on Current
        3. 2.3.4.3 Phase Shift
        4. 2.3.4.4 Capacitor Selection
        5. 2.3.4.5 Soft Switching Range
        6. 2.3.4.6 Switching Frequency
        7. 2.3.4.7 Transformer Selection
        8. 2.3.4.8 SiC MOSFET Selection
      5. 2.3.5 Loss Analysis
        1. 2.3.5.1 Design Equations
        2. 2.3.5.2 SiC MOSFET and Diode Losses
        3. 2.3.5.3 Transformer Losses
        4. 2.3.5.4 Inductor Losses
        5. 2.3.5.5 Gate Driver Losses
        6. 2.3.5.6 Efficiency
        7. 2.3.5.7 Thermal Considerations
  8. 3Circuit Description
    1. 3.1 Power Stage
    2. 3.2 DC Voltage Sensing
      1. 3.2.1 Primary DC Voltage Sensing
      2. 3.2.2 Secondary DC Voltage Sensing
    3. 3.3 Current Sensing
    4. 3.4 Power Architecture
      1. 3.4.1 Auxiliary Power Supply
      2. 3.4.2 Isolated Power Supply for Sense Circuits
    5. 3.5 Gate Driver
      1. 3.5.1 Gate Driver Circuit
      2. 3.5.2 Gate Driver Bias Power Supply
      3. 3.5.3 Gate Driver Discrete Circuits - Short-Circuit Detection and Two Level Turn Off
  9. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Required Hardware and Software
      1. 4.1.1 Hardware
      2. 4.1.2 Software
        1. 4.1.2.1 Getting Started With Software
        2. 4.1.2.2 Pin Configuration
        3. 4.1.2.3 PWM Configuration
        4. 4.1.2.4 High-Resolution Phase Shift Configuration
        5. 4.1.2.5 ADC Configuration
        6. 4.1.2.6 ISR Structure
    2. 4.2 Test Setup
    3. 4.3 PowerSUITE GUI
    4. 4.4 LABs
      1. 4.4.1 Lab 1
      2. 4.4.2 Lab 2
      3. 4.4.3 Lab 3
      4. 4.4.4 Lab 4
      5. 4.4.5 Lab 5
    5. 4.5 Test Results
      1. 4.5.1 Open-Loop Performance
      2. 4.5.2 Closed-Loop Performance
  10. 5Design Files
    1. 5.1 Schematics
    2. 5.2 Bill of Materials
    3. 5.3 PCB Layout Recommendations
      1. 5.3.1 Layout Prints
    4. 5.4 Altium Project
    5. 5.5 Gerber Files
    6. 5.6 Assembly Drawings
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7Terminology
  13. 8About the Author
  14. 9Revision History

Lab 2

In the lab 2 build, the board is excited in open-loop fashion with a specified frequency (100 kHz) and phase shift. The phase shift can be changed through the watch window. The phase shift is controlled with the DAB_pwmPhaseShiftPrimSec_pu variable. This build verifies the sensing of feedback values from the power stage, operation of the PWM gate driver, HW protection, and ensures there are no hardware issues. Additionally, calibrate the input and output voltage sensing in this build.

  • Test Setup for Lab 2

    The hardware for this reference design is composed of the following boards:

    • One TIDA-010054 power board
    • Four TIDA-010054 gate driver cards
    • Two TIDA-01606 ISOHV sense cards
    • One TMDSCNCD280049C control card
    • Mini USB cable
    • Laptop
  • The following test equipment is needed to power and evaluate the DUT
    • 10-kW DC source capable of delivering voltage between 700 V–800 V at required current
    • 10-kW resistive load bank
    • Power analyzer
    • Dual channel +15-V, 4-V auxiliary bench power supply
    • Oscilloscope
    • Isolated voltage probes and current probe
    GUID-20210823-SS0I-RCQQ-G22Z-QDD7R0MG9GPH-low.gif Figure 4-20 Lab 2 Test Setup
    Software Setup for Lab 2

    The following defines are set in the "settings.h" file for this build. The settings can be defined by selecting Lab 2: Open Loop PWM with Protection in the drop-down menu of Project Options from PowerSUITE GUI.

    GUID-20210818-SS0I-SM9Q-631Z-R2PZ9Z0SJH69-low.png Figure 4-21 Lab 2 Software Setup
    1. Run the project by clicking the green run button in CCS
    2. Populate the required variables in the watch window by loading javascript ' setupdebugenv_lab2.js' in the scripting console
      GUID-20210818-SS0I-P2N3-MZJQ-GTV2NZZS14CJ-low.png Figure 4-22 Lab 2 Watch View Configuration
    3. Enable PWM by writing “1” to the DAB_clearTrip variable
    4. In the watch view, check if the DAB_vPrimSensed_Volts, DAB_iPrimSensed_Amps, DAB_vSecSensed_Volts, and DAB_iSecSensed_Amps variables are updating periodically
      Note: Because no power is applied at this point, these are close to zero.
    5. Now, slowly increase the input VPRIM DC voltage from 0 V to 800 V. Make sure DAB_vPrimSensed_Volts displays the correct values.
    6. By default, the DAB_pwmPhaseShiftPrimSec_pu variable is set to 0.032. Vary this phase shift slowly in steps of 0.002 pu and observe the change in voltage at the output of converter. Care must be taken to not increase the phase shift very high as it can boost the output voltage greater than the input voltage and can lead to breakdown of MOSFETs at maximum applied voltage

      .

  • Measure SFRA Plant for Voltage Loop
    1. The SFRA is integrated in the C2000Ware-DigitalPower-SDK kit to measure the plant response which can then be used to design a compensator. Run the SFRA by clicking on the SFRA icon. The SFRA GUI opens.
    2. Select the options for the device on the SFRA GUI; for example, for F280049, select floating point. Click the Setup Connection button. In the pop-up window, uncheck the boot-on-connect option and select an appropriate COM port. Select the OK button. Return to the SFRA GUI and click the Connect button.
    3. The SFRA GUI connects to the device. A SFRA sweep can now be started by clicking the Start Sweep button. The complete SFRA sweep takes a few minutes to complete. Monitor the activity in the progress bar on the SFRA GUI or by checking the flashing blue LED on the back of the control card, which indicates UART activity.
      GUID-20210818-SS0I-JWNZ-FB3S-LZRT9QGZFJKR-low.png
      Test condition: VIN = 600 V, VOUT = 425 V, IIN = 4.72 A, Phase shift = 0.056, SFRA Amplitude = 0.002
      Figure 4-23 Lab 2 SFRA Plant Plot for the Open Voltage Loop Test
    4. The Frequency Response Data ("SFRA.csv") is saved in the project folder, under an SFRA Data Folder, and is time-stamped with the time of the SFRA run. SFRA can be run at different frequency setpoints to cover the range of operation of the system. A compensator is designed using these measured plots through compensator designer.

      Inside ISR1, the SFRA injects small signal perturbations in phase and observes the sensed output voltage variations. The following lines of code inside the dab.h file perform the SFRA signal injection and collection.

      GUID-20210818-SS0I-DWJJ-SFXD-MFCLFHX9DX7S-low.pngFigure 4-24 Lab 2 Code for SFRA Signal Injection
  • Measure SFRA Plant for Current Loop
    1. Follow the same steps as in voltage loop to get started with SFRA measurement for current loop.
    2. In the PowerSUITE GUI under SFRA tab, choose "current" prior to running the SFRA current loop.
      GUID-20210818-SS0I-CJZR-SQMR-TNJ995DJGKJZ-low.pngFigure 4-25 Lab 2 Code Defines SFRA Current Loop
    3. Inside ISR1, the SFRA injects small signal perturbations in phase and observes the sensed output current variations. The following lines of code inside the dab.h file perform the SFRA signal injection and collection.
      GUID-20210818-SS0I-NLK3-TBBQ-KMNLG1ZJFRNF-low.pngFigure 4-26 Lab 2 Code for SFRA Signal Injection
    4. Measure the plant response from SFRA GUI. The open loop and plant response are stored in the file named 'SFRA.csv'. Use this file to tune the compensator for the current loop.
      GUID-20210818-SS0I-52VM-NV9L-WXMVWBBT0M3B-low.jpgFigure 4-27 Lab 2 SFRA Plant Plot for the Open Current Loop Test
      Note: The current is sensed by AMC3301 at the battery (load) side
  • Protection validation

    The limits for overcurrent and overvoltage protection can be modified from PowerSUITE GUI.

    #define DAB_ISEC_TRIP_LIMIT ((float32_t) 8.0)
    #define DAB_IPRIM_TRIP_LIMIT ((float32_t) 1.5)
    #define DAB_IPRIM_TANK_TRIP_LIMIT ((float32_t)35.0)
    #define DAB_VSEC_TRIP_LIMIT ((float32_t)500)
    Note: Secondary tank current and Primary overvoltage protection are not supported in the current HW.

    Set the limits to a lower value and adjust the source, the load, or both to exceed the thresholds to validate the trips.

    GUID-20210818-SS0I-4W4D-QZDS-TT26M6JR9R51-low.png
    Primary - tank overcurrent protection, limit set = 4 A
    Figure 4-28 Lab 2 Primary - Tank Overcurrent Protection
    GUID-20210818-SS0I-L30P-3ZRD-09TCWSNRQWCS-low.png
    Primary (input) overcurrent protection, limit set = 1 A
    Figure 4-29 Lab 2 Primary (Input) Overcurrent Protection
    GUID-20210818-SS0I-ZQKR-SF8L-LK9BRMXNCHT6-low.png
    Secondary (resistive load) overcurrent protection, limit set = 1.5 A
    Figure 4-30 Lab 2 Secondary (Resistive Load) Overcurrent Protection
    GUID-20210818-SS0I-LVVJ-4QQQ-5SZ5BQG2NDZJ-low.png
    DAB_VSEC_TRIP_LIMIT = 75 V
    Figure 4-31 Lab 2 Secondary Overvoltage Protection
    GUID-20210818-SS0I-CKZB-XJLD-GPDTKFQRMFXL-low.png
    DAB_VSEC_TRIP_LIMIT = 75 V (Zoomed In)
    Figure 4-32 Lab 2 Secondary Overvoltage Protection(Zoomed In)

    The previous waveforms show PWM is shut off by the comparator sub-system during fault events. The type of fault is displayed in the watch window (Figure 4-33) through variable "DAB_tripFlag". The trip can be reset by selecting "noTrip" under the drop-down menu and re-enabling the PWM by writing “1” to the DAB_clearTrip variable. Make sure the fault condition is removed before re-enabling the PWM.

    GUID-20210823-SS0I-JRZV-16X1-TNFJJLXPQXBW-low.png Figure 4-33 Lab 2-14