SPRABJ8B September   2022  – November 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2 V
        2. 2.5.1.2 Digital/Analog I/O Power 3.3 V
    6. 2.6 e-Fuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 OSPI/QSPI Memory Implementation
    3. 5.3 ROM OSPI/QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Analog Peripherals
    1. 9.1 General Analog Peripheral Routing Guidelines
      1. 9.1.1 Resolver ADC Routing Guidelines
  13. 10Layer Stackup
    1. 10.1 Key Stackup Features
  14. 11Vias
  15. 12BGA Power Fan-Out and Decoupling Placement
    1. 12.1 Ground Return
    2. 12.2 1.2 V Core Digital Power
      1. 12.2.1 Key Layout Considerations
    3. 12.3 3.3 V Digital and Analog Power
      1. 12.3.1 Key Layout Considerations
    4. 12.4 1.8 V Digital and Analog Power
      1. 12.4.1 Key Layout Considerations
  16. 13References
  17.   Revision History

6 JTAG Emulators and Trace

The AM263x and AM263Px MCUs support multiple different classes of JTAG emulators with or without additional ARM Trace capture capabilities.

For out of box convenience the LP-AM263, LP-AM263P, TMDSCNCD263, and TMDSCNCD263P EVM designs implement an onboard XDS110 emulator with JTAG and auxiliary UART-USB bridge is implemented with a TI TM4C MCU and high-voltage isolation. However, for actual custom systems, a simpler JTAG/Trace debug header should be implemented. This allows for external JTAG and Trace pods to be attached to the system as needed during development. The header can then be removed entirely or depopulated for full production of the system to save cost.

One popular, JTAG and Trace implementation is the MIPI industry standard MIPI-60 shown in [13]. This is based on the Samtec QSH-030-01-L-D-A. This implementation is compatible with TI XDS560v2 JTAG/Trace pods as well as other third-party JTAG/Trace pods. Additional, TI JTAG debugger connections can be found in [14].

GUID-20220808-SS0I-GHKD-G7GP-LKGPBQMSQWWZ-low.svg Figure 6-1 Example MIPI-60 JTAG and 16-Bit Trace Implementation

Additional, non-TI JTAG debug and Trace systems are still being tested. Further guidance is planned in future revisions of this document.