SPRABJ8B September   2022  – November 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2 V
        2. 2.5.1.2 Digital/Analog I/O Power 3.3 V
    6. 2.6 e-Fuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 OSPI/QSPI Memory Implementation
    3. 5.3 ROM OSPI/QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Analog Peripherals
    1. 9.1 General Analog Peripheral Routing Guidelines
      1. 9.1.1 Resolver ADC Routing Guidelines
  13. 10Layer Stackup
    1. 10.1 Key Stackup Features
  14. 11Vias
  15. 12BGA Power Fan-Out and Decoupling Placement
    1. 12.1 Ground Return
    2. 12.2 1.2 V Core Digital Power
      1. 12.2.1 Key Layout Considerations
    3. 12.3 3.3 V Digital and Analog Power
      1. 12.3.1 Key Layout Considerations
    4. 12.4 1.8 V Digital and Analog Power
      1. 12.4.1 Key Layout Considerations
  16. 13References
  17.   Revision History

2.5.1.1 Core Digital Power 1.2 V

Z11 simulations were performed on the 1.2 V core digital power net of the LP-AM263 LaunchPad EVM to verify transient power margin. The simulation domain included the:

  • AM263x BGA (UI) 1.2 V digital and GND return fan-out
  • Internal PCB 1.2 V and GND return planes
  • Decoupling placed on the 1.2 V power net,
  • U29 buck regulator output LC filter up to switch node

These simulations were done iteratively with multiple capacitor BOM changes made between each iteration. Each iteration was characterized primarily by the maximum and minimum frequency bandwidth below Ztarget (see above sections) and the BOM selection changed to maximize bandwidth and maximum Ztarget margin. Only the initial and final chosen BOM iterations are shown in Figure 2-12 and Figure 2-13.

GUID-20220808-SS0I-LNX9-CLCG-8JK33QX4K9CQ-low.png Figure 2-12 AM263x LaunchPad PDN Simulations – 1.2 V Core Power Simulation Domain
GUID-20220808-SS0I-S0FQ-XF1T-BVML6NRBBHPX-low.png Figure 2-13 AM263x LaunchPad PDN Simulations – 1.2 V Core Power Simulated Z11
  • AM263x LaunchPad PDN Simulations – 1.2 V Core Power Simulated Z11
    • This resulted in the marker (m2) point of 5.5 mΩ
    • Ztarget requirement of 36mOhm maintained from 50 KHz to 63 MHz
    • Major difference in BOM was replacing all 0.1 µF BGA and local decoupling capacitors with 1.0 µF capacitors this entirely removed the 10 MHz resonant point in the PDN impedance spectrum
  • PROC111E1_20210921 Initial simulations
    • Major resonance at 10 MHz eliminated almost all margin against 36 mΩ Ztarget requirement