SPRADA9C August   2024  – October 2025 AM62P , AM62P-Q1

 

  1.   1
  2.   ABSTRACT
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Before Getting Started With the Custom Board Design
    2. 1.2 Processor-Specific SDK
    3. 1.3 Peripheral Circuit Implementation - Compatibility Between Processor Families
    4. 1.4 Selection of Required Processor OPN (Orderable Part Number)
      1. 1.4.1 Processor Support for Secure Boot and Functional Safety
    5. 1.5 Technical Documentation
      1. 1.5.1 Updated SK Schematic With Design, Review and Cad Notes Added
      2. 1.5.2 Collaterals on TI.com, Processor Product Page
      3. 1.5.3 Schematic Design Guidelines and Schematic Review Checklist - Processor Family Specific User's Guide
      4. 1.5.4 Updates to Hardware Design Considerations User's Guide
      5. 1.5.5 Processor and Peripherals Related FAQs to Support Custom Board Designs
    6. 1.6 Custom Board Design Documentation
    7. 1.7 Processor and Processor Peripherals Design Related Queries During Custom Board Design
  5. 2 Custom Board Design Block Diagram
    1. 2.1 Developing the Custom Board Design Block Diagram
    2. 2.2 Configuring the Boot Mode
    3. 2.3 Configuring the Processor Pins Functionality (PinMux Configuration)
  6. 3 Power Supply
    1. 3.1 Power Supply Architecture
      1. 3.1.1 Integrated Power Architecture
      2. 3.1.2 Discrete Power Architecture
    2. 3.2 Processor Supply (Power) Rails (Operating Voltage)
      1. 3.2.1 Supported Low-Power Modes
        1. 3.2.1.1 Partial IO Support for CAN/GPIO/UART Wakeup
      2. 3.2.2 Core Power Supply
      3. 3.2.3 Peripherals Power Supply
      4. 3.2.4 Dual-Voltage IO Supply for IO Group (Processor) Power Supply
      5. 3.2.5 Dynamic Voltage Switching Dual-Voltage Power Supply
      6. 3.2.6 VPP (eFuse ROM Programming) Power Supply
      7. 3.2.7 Internal LDOs for IO Supply for IO Groups (Processor)
    3. 3.3 Power Supply Filtering
    4. 3.4 Power Supply Decoupling and Bulk Capacitors
      1. 3.4.1 Note on PDN Target Impedance
    5. 3.5 Power Supply Sequencing
    6. 3.6 Power Supply Diagnostics (Using Processor Supported External Input Voltage Monitors)
    7. 3.7 Power Supply Diagnostics (Monitoring Using External Monitoring Circuit (Devices))
    8. 3.8 Custom Board Current Requirements Estimation and Supply Sizing
  7. 4 Processor Clock (Input and Output)
    1. 4.1 Processor Clocking (External Crystal or External Oscillator)
      1. 4.1.1 WKUP_LFOSC0 Connection When Unused
      2. 4.1.2 MCU_OSC0 and WKUP_LFOSC0, Crystal Selection
      3. 4.1.3 LVCMOS Compatible Digital Clock Input Source
    2. 4.2 Processor Clock Outputs
      1. 4.2.1 Observation Clock Outputs
    3. 4.3 Clock Tree Tool
  8. 5 JTAG (Joint Test Action Group)
    1. 5.1 JTAG / Emulation
      1. 5.1.1 Configuration of JTAG / Emulation
        1. 5.1.1.1 BSDL File
      2. 5.1.2 Implementation of JTAG / Emulation
      3. 5.1.3 Connection Recommendations for JTAG Interface Signals
      4. 5.1.4 Debug Boot Modes and Boundary Scan Compliance
  9. 6 Configuration (Processor) and Initialization (Processor and Device)
    1. 6.1 Processor Reset
    2. 6.2 Latching of Processor Boot Mode Configuration Inputs
    3. 6.3 Resetting of the Attached Device
    4. 6.4 Watchdog Timer
  10. 7 Processor - Peripherals Connection
    1. 7.1  Supported Processor Cores and MCU Cores
    2. 7.2  Selecting Peripherals Across Domains
    3. 7.3  Memory Controller (DDRSS)
      1. 7.3.1 Processor DDR Subsystem and Device Register Configuration
      2. 7.3.2 Calibration Resistor Connection for DDRSS
      3. 7.3.3 Attached Memory Device ZQ and Reset_N (Memory Device Reset) Connection
    4. 7.4  Media and Data Storage Interfaces (MMC0, MMC1, MMC2, OSPI0/QSPI0 and GPMC0)
    5. 7.5  Ethernet Interface
      1. 7.5.1 Common Platform Ethernet Switch 3-port Gigabit (CPSW3G0)
    6. 7.6  Programmable Real-Time Unit Subsystem (PRUSS)
    7. 7.7  Universal Serial Bus (USB) Subsystem
    8. 7.8  General Connectivity Peripherals
      1. 7.8.1 Inter-Integrated Circuit (I2C) Interface
    9. 7.9  Display Subsystem (DSS)
    10. 7.10 CSI-Rx (Camera Serial interface)
    11. 7.11 Real-Time Clock (RTC) Module
    12. 7.12 Connection of Processor Power Supply Pins, IOs and Peripherals When not Used
      1. 7.12.1 External Interrupt (EXTINTn)
      2. 7.12.2 RSVD Reserved Pins (Signals)
    13. 7.13 SK Specific Circuit Implementation (Reuse)
  11. 8 Interfacing of Processor IOs (LVCMOS or SDIO or Open-Drain, Fail-Safe Type IO Buffers) and Performing Simulations
    1. 8.1 IBIS Model
    2. 8.2 IBIS-AMI Model
  12. 9 Processor Current Draw and Thermal Analysis
    1. 9.1 Power Estimation
    2. 9.2 Maximum Current Rating for Different Supply Rails
    3. 9.3 Supported Power Modes
    4. 9.4 Thermal Design Guidelines
      1. 9.4.1 Thermal Model
      2. 9.4.2 Voltage Thermal Management Module (VTM)
  13. 10Schematic:- Capture, Entry and Review
    1. 10.1 Custom Board Design Passive Components and Values Selection
    2. 10.2 Custom Board Design Electronic Computer Aided Design (ECAD) Tools Considerations
    3. 10.3 Custom Board Design Schematic Capture
    4. 10.4 Custom Board Design Schematic Review
  14. 11Floor Planning, Layout, Routing Guidelines, Board Layers and Simulation
    1. 11.1 Escape Routing for PCB Design
    2. 11.2 LPDDR4 Design and Layout Guidelines
    3. 11.3 High-Speed Differential Signal Routing Guidelines
    4. 11.4 Processor-Specific SK Board Layout
    5. 11.5 Custom Board Layer Count and Layer Stack-up
      1. 11.5.1 Simulation Recommendations
    6. 11.6 DDR-MARGIN-FW
    7. 11.7 Reference for Steps to be Followed for Running Board Simulation
    8. 11.8 Software Development Training (Academy) for Processors
  15. 12Custom Board Assembly and Testing
    1. 12.1 Custom Board Bring-up Tips and Debug Guidelines
  16. 13Processor (Device) Handling and Assembly
    1. 13.1 Processor (Device) Soldering Recommendations
      1. 13.1.1 Additional References
  17. 14Terminology
  18. 15References
    1. 15.1 Processor-Specific (AM62P, AM62P-Q1)
    2. 15.2 Common
  19. 16Revision History

7.4 Media and Data Storage Interfaces (MMC0, MMC1, MMC2, OSPI0/QSPI0 and GPMC0)

The processor family supports x3 (three) Multi-Media Card/Secure Digital (MMC/SD/SDIO) (8b (4b) + 4b + 4b) instances.

MMC0 supports 8-bit eMMC (MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51)) interface. eMMC interface implemented internal to the processor is a dedicated hard macro PHY. The MUX MODE, DSIS, and MUX MODE AFTER RESET columns in the Pin Attributes (AMH Package) table of the device-specific data sheet is blank since the pins (interface) are implemented with a hard macro PHY (does not support pin multiplexing). For supported speeds, see the MMC0 - eMMC Interface section of device-specific data sheet. The required pulls for the eMMC interface as per the JEDEC standard is implemented internal to the processor eMMC hard macro PHY.

Review eMMC related silicon errata AM62Px Sitara™ Processors Silicon Errata, Silicon Revision 1.0, 1.1. The recommendation is to connect VDDA_0P85_DLL_MMC0 (1J1, VDDR_CORE), VDD_MMC0 (1K3, VDDR_CORE) and VDDR_CORE to the same supply source to support future enhancements (including support for HS400 eMMC application) for silicon revision 1.2 and above. For SR1 and SR1.1, when eMMC interface is used and VDD_CORE is 0.85V, the recommendation is to connect VDDA_0P85_DLL_MMC0 (1J1, VDDR_CORE), VDD_MMC0 (1K3, VDDR_CORE) and VDDR_CORE to same source powering VDD_CORE. For SR1 and SR1.1, when eMMC interface is used and VDD_CORE is 0.75V, the recommendation is to connect VDDA_0P85_DLL_MMC0 (1J1, VDDR_CORE), VDD_MMC0 (1K3, VDDR_CORE) and VDDR_CORE to 0.85V supply source. For SR1 and SR1.1, when eMMC is not used the recommendation is to connect VDDA_0P85_DLL_MMC0 (1J1, VDDR_CORE), VDD_MMC0 (1K3, VDDR_CORE) to VDD_CORE.

For more information on eMMC memory interface HS400 support, see the following FAQ:

[FAQ] AM62P / AM62P-Q1 Custom board hardware design – Power supply connection and Board layout recommendations to support HS400

For more information on eMMC memory interface, see the following FAQ:

[FAQ] AM625 / AM623 / AM620-Q1 / AM62L / AM64x/ AM243x (ALV) / AM62Ax / AM62D-Q1 / AM62Px Design Recommendations / Commonly Observed Errors during Custom board hardware design – eMMC MEMORY Interface

For information on the supported speeds, see the following FAQ:

[FAQ] AM623: Can eMMC0 support DDR50 mode

For information on supported interface on the MMC0 port, see the following FAQ:

[FAQ] AM62A3: Any way to get 2 eMMC interfaces?

For information related to eMMC capability to pause the clock when there are no transfers, see the following FAQ:

[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP: Is the eMMC clocks maintained when read and write operations are finished ?

The FAQ is generic and can also be used for AM62P, AM62P-Q1 processor family.

For connecting the MMC0 interface signals when not used, see the Pin Connectivity Requirements section of device-specific data sheet.

Refer to the silicon errata for eMMC related erratas.

MMC1/MMC2 supports 4-bit SD card interface including support for UHS-I SD card. MMC1 is recommended for implementing SD card interface since MMC1 supports SD card boot mode, MMC1 CLK, CMD, and DAT[3:0] signal functions have been implemented with SDIO buffers and are powered by (referenced to) VDDSHV5. VDDSHV5 can be operated at 1.8V or 3.3V (dynamically switched). MMC1 SDCD and SDWP signal functions are implemented with LVCMOS buffers and are powered by (referenced to) VDDSHV0, which can be operated at fixed 3.3V or 1.8V. The logic state of the MMC1_SDCD and MMC1_SDWP inputs to the host is not recommended to be changed when IO operating voltage for SD card changes to support UHS-I SD card. The required pulls for the SD card interface as per the SD card specifications is required to be implemented external to the processor. An external pulldown for the clock input near to the memory clock input pin is recommended.

MMC1/MMC2 supports 4-bit embedded SDIO interface. MMC2 is recommended for implementing embedded SDIO interface. MMC2 CLK, CMD, and DAT[3:0] signal functions have been implemented with SDIO buffers and are powered by (referenced to) VDDSHV6. VDDSHV6 can be operated at 1.8V or 3.3V (dynamically switched). MMC2 SDCD and SDWP signal functions are implemented with LVCMOS buffers and are powered by (referenced to) VDDSHV6 (VDDSHV0), which can be operated at fixed 3.3V or 1.8V. Refer Signal Description section of the device-specific data sheet for supported pin assignments. The MMC2 pin assignments are different compared to MMC1 because MMC2 is expected to be used with on-board fixed operating voltage SDIO devices similar to Wi-Fi or Bluetooth transceivers. For supported speeds, see the MMC1/MMC2 -SD/SDIO Interface section of device-specific data sheet, refer SK for implementation. Pullups (as required, verify the attached device recommendations including supported pulls) for the SDIO interface is required to be implemented external to the processor. An external pulldown (as required, verify the attached device recommendations including supported pulls) for the clock input near to the memory clock input pin is recommended.

For more information, see the following FAQs:

[FAQ] AM625 / AM623 / AM620-Q1 / AM62L / AM64x/ AM243x (ALV) / AM62Ax / AM62D-Q1 / AM62Px Design Recommendations / Commonly Observed Errors during Custom board hardware design –SD card Interface

[FAQ] AM62A7 / AM62A3 / AM62A1-Q1 / AM62D-Q1: Why is MMC1 powered by two different voltage supplies, VDDSHV0 and VDDSHV5?

[FAQ] AM62A7-Q1: how to connect the pin net VDDSHV4, VDDSHV5, and VDDSHV6 if SD card is not used

The FAQs are generic and can also be used for AM62P, AM62P-Q1 processor family.

For MMC1/MMC2, UHS-I SDR50, UHS-I SDR104 receive modes require data training to center the data capture to the center of the data valid window. The timing requirements are not fixed to specific values. The required DLL software configuration settings for MMC1/2 timing modes is provided in the below table:

MMC1/MMC2 DLL Delay Mapping for all Timing Modes of device-specific data sheet.

For more information, see the following FAQ:

[FAQ] AM625 / AM623 / AM620-Q1 / AM625-Q1 / AM625SIP: UHS-I SDR104 Receive mode timing

The FAQ is generic and can also be used for AM62P, AM62P-Q1 processor family.

The processor family supports x1 Octal Serial Peripheral Interface (OSPI0) instance that can be configured for OSPI0 or QSPI0 interface. The recommendation is to follow the SK schematic implementation to interface the OSPI0 interface to a memory device (OSPI or QSPI), addition of series resistor for OSPI0_CLK (for control of possible reflection), pulldown for OSPI0_CLK, pullup for data and CS signals, and implementation of attached memory device reset logic. OSPI0 supports connecting to a x1 (single) attached device.

Refer to the device-specific TRM to connect the supported CS (chip select) to the attached memory device when boot functionality is required to be supported.

OSPI0 supports two data capture modes, PHY mode and Tap mode. To better understand the supported modes, refer to the OSPI, OSPI0 sub-section in the Timing and Switching Characteristics section in the Specifications chapter of the device-specific data sheet.

For more information on OSPI or QSPI memory interface, see the following FAQs:

[FAQ] AM625 / AM623 / AM620-Q1 / AM62L / AM62A / AM62D-Q1 / AM62P Design Recommendations / Commonly Observed Errors during Custom board hardware design – OSPI/QSPI MEMORY Interface

[FAQ] OSPI FAQ for Sitara/Jacinto devices

The processor family supports x1 General-Purpose Memory Controller (GPMC) interface instance that can be interfaced to NAND flash using 8-bit or 16-bit NAND flash interface signals or NOR flash using supported parallel memory interface (Synchronous or Asynchronous) options listed in the device-specific data sheet and Device Comparison table.

Processor IO buffers are off during reset and after reset. Parallel pulls are recommended for any of the processor IOs (Memory interface signals) that can float (to prevent the attached device inputs from floating until driven by the host).

For more information, see the Memory Interfaces section in the Peripherals chapter of the device-specific TRM.