Typically, there are four tables written into the memory in advance, including an encoding 5b-6b table, encoding 3b-4b table, decoding 6b-5b table, and decoding 4b-3b table. Data has to be encoded using a look-up table (LUT) prior to transmission and decoded with the LUT after receiving. To demonstrate encoding and decoding data, the Sitara™ AM243x LaunchPad™ development kit is selected as the device for verification. The HW_WR_REG8 function can be used to put the four tables into PRU Dynamic Random Access Memory (DRAM) with different offset addresses using the C code of the Arm® core project, see also the following code.

uint32_t enc_5b6b = CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE + ENC_5B6B_OFFS;
uint32_t enc_3b4b = CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE + ENC_3B4B_OFFS;
uint32_t dec_5b6b = CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + DEC_5B6B_OFFS;
uint32_t dec_3b4b = CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE + DEC_3B4B_OFFS;
    //Encoding LUTs (input MSB first, output LSB first)
    //LUT 5b/6b encoding
HW_WR_REG8(enc_5b6b + 0x00, 0x18);
...
    //LUT 3b/4b encoding
HW_WR_REG8(enc_3b4b + 0x00, 0x04);
...
    //Decoding LUTs (input LSB first, output MSB first)
    //LUT 6b/5b decoding
HW_WR_REG8(dec_5b6b + 0x00, INVAL);
...
    //LUT 4b/3b decoding
HW_WR_REG8(dec_3b4b + 0x00, INVAL);
...

Data can be encoded by the LUT in a PRU firmware project using load byte burst (LBBO) instruction. The LBBO instruction is used to read a block of data from memory into the register file. The REG_TMP11 register stores the LUT header address and REG_ENC register stores the original data and encoded data. See the following code of encode 8-bit data (0x34):

Ldi REG_ENC.b0, 0x14                       ;raw data 5b LSB
ldi REG_TMP11, (PDMEM00+LUT_5b6b_ENC)      ; TEMP11 for 5b/6b LUT header
lbbo &REG_ENC.b3, REG_TMP11, REG_ENC.b0, 1 ; FNC.b0 for original 5 bit -data, ENC.b3 for encoded 6 bit
ldi REG_ENC.b1, 0x01                       ; raw data 3b MSB
ldi REG_TMP11, (PDMEM00+LUT_3b4b_ENC)      ; TEMP11 for 3b/4b LUT header
lbbo &REG_ENC.b2, REG_TMP11, REG_ENC.b1, 1 ; FNC.b1 for original 3 bit -data, ENC.b2 for encoded 4 bit

The lower five bits of 0x34 is 0x14 and these bits load immediately into byte 0 of REG_ENC. After the LUT, the six encoded bits are written into byte 3 of REG_ENC. The higher three bits of 0x34 is 0x01 and these bits load immediately into byte 1 of REG_ENC. After LUT, the four encoded bits are written into the byte 2 of REG_ENC.

Figure 2-1 shows the REG_ENC register distribution for the original data and encoded data.

Figure 2-1 REG_ENC Encoding Register Distribution

The decoding process is nearly identical to the encoding process. The decoding process also uses LBBO instructions with the LUT for decoding after receiving the encoded data. The REG_TMP11 register stores the LUT header address and the REG_DEC register stores the encoded data and decoded data.

The six encoded bits are received and moved into byte 1 of REG_DEC. After the LUT, the five decoded bits are written into the byte 2 of REG_DEC. The higher four bits are received and moved into byte 0 of REG_DEC. After LUT, the three decoded bits are written into byte 3 of REG_DEC. To combine the 10 bits of data from two bytes of the register into eight bits of data, byte 3 of REG_DEC needs to be shift left by five bits and logically added with byte 2 of REG_DEC. The final decoded eight bits of data is stored in byte 0 of REG_DEC. The following code shows the decoding process.

ldi REG_TMP11, (PDMEM00+LUT_5b6b_DEC)      ; TEMP11 for 5b/6b LUT header
lbbo &REG_DEC.b2, REG_TMP11, REG_DEC.b1, 1 ; decode 6b
ldi REG_TMP11, (PDMEM00+LUT_3b4b_DEC)      ; TEMP11 for 3b/4b LUT header
lbbo &REG_DEC.b3, REG_TMP11, REG_DEC.b0, 1 ; decode 4b
lsl REG_DEC.b3, REG_DEC.b3, 5              ; shift left 5 bit
add REG_DEC, REG_DEC.b2, REG_DEC.b3        ; combine to 8 bit data

Figure 2-2 shows the REG_DEC register distribution for encoded data and decoded data.

Figure 2-2 REG_DEC Decoding Register Distribution