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  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to 8b-10b Line Coding
  5. 2PRU Implementation for Data Transmitting and Receiving
    1. 2.1 Encoding and Decoding Data
    2. 2.2 PRU Module Interface and GPIO Mode
    3. 2.3 PRU GPIO Shift-out and Shift-in Mode for Communication
    4. 2.4 Three-channel Peripheral Interface for Communication
    5. 2.5 LVDS and M-LVDS Interface
  6. 3System Solution With CRC Module and Over-head Optimization
    1. 3.1 PRU CRC16/32 Module
    2. 3.2 Encode and Decode Over-head Optimization
  7. 4Verification
  8. 5Summary
  9. 6References

2.5 LVDS and M-LVDS Interface

Low-voltage Differential Signaling (LVDS) devices generally comply with the American National Standards Institute (ANSI) standard TIA/EIA-644. And the Multipoint Low Voltage Differential Signaling (M-LVDS) comply with ANSI TIA/EIA-899. Table 2-1 highlights some of the important specifications for drivers and receivers between LVDS and M-LVDS.

Table 2-1 Comparison of LVDS Specification
Parameter TIA/EIA-644-A (LVDS REV A) TIA/EIA-899 (M-LVDS) Unit
Driver characteristics
Offset voltage: Vos (maximum) 1375 2100 mV
Offset voltage: Vos (minimum) 1125 300 mV

Differential output voltage: Vod (maximum)

 454 (100 Ω) 650 (50 Ω) mV
Differential output voltage: Vod (minimum) 247 (100 Ω) 480 (50 Ω) mV
Offset voltage variation: Vospp 150 150 mV
Short circuit current: Ios 12/24 43 mA
Differential voltage change: ΔVod 50 50 mV
Offset voltage change: ΔVos 50 50 mV
Transition time: tr/tf (minimum) 260 1000 ps
Receiver characteristics
Ground potential difference: Vgpd ±1 ±1 V
Input leakage current: Iin 20 20 μA
Differential input leakage current: Iid 6 4 μA
Input voltage range: Vin 0 to 2.4 -1.4 to 3.8 V
Input threshold: Vith 100 50 mV

Intra drive communication designs require high speed, low power and electromagnetic compatibility. Hence, LVDS devices provide a wide range of solutions for intra drive communication designs from point-to-point to multidrop data transmission. The data transfer rate can range from up to 1500Mbps with a 100-meter cable length and only required 1.2 mW power consumption. Differential signals also help by having high noise immunity. The DS90x series for LVDS and SN65MLVDSx series for M-LVDS from Texas Instruments incorporates a wide variety of single and multichannel devices for designers. Moreover, TI’s ISO7821LLx series provides reinforced isolation with LVDS interface when required in intra drive designs, especially for cold-hot side control applications. The intra drive communication block diagram with LVDS interface and PRU is shown as Figure 2-10.

GUID-20230606-SS0I-T6MH-NBF2-T27BJBDWCCHD-low.svg Figure 2-10 Intra Drive Communication Block Diagram With LVDS Interface and PRU

To verify the latency of LVDS transceivers and isolators, a 100 MHz clock signal is sent by PRU_GPO using the DS90LV049+ISO7821LL for LVDS interface and SM65MLVDS203+ISO7840 for M-LVDS interface. Figure 2-11 and Figure 2-12 show the latency for LVDS interface is 18ns and for M-LVDS interface is 22ns.

GUID-20230606-SS0I-NGR4-65B9-414CQQ0NCF8Q-low.png Figure 2-11 18ns Latency for DS90LV049 and ISO7821LL LVDS Interfaces
GUID-20230606-SS0I-82LB-LMTH-HBDFFRQ4PBQH-low.png Figure 2-12 22ns Latency for SN65MLLVDS203 and ISO7840 M-LVDS Interfaces