SPRADQ5 March   2025 AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction of AC or Servo Drive Hot-Side Control Architecture
  5. 2PRU and FSI Implementation for Time Synchronization and Data Transmitting
    1. 2.1 Importance of Clock in Industrial Systems With MCUs
    2. 2.2 IEP Timer Interface
    3. 2.3 PRU_ICSSG Task Manger
    4. 2.4 Fast Serial Interface
    5. 2.5 Two-Chip System Scheme for Time Synchronization and Data Transmitting
      1. 2.5.1 Device 1 Configuration
        1. 2.5.1.1 Pad Configuration
        2. 2.5.1.2 Clock Source Configuration
        3. 2.5.1.3 IEP Timer Configuration
        4. 2.5.1.4 Task Manager Configuration
      2. 2.5.2 Device 2 Configuration
        1. 2.5.2.1 Pad Configuration
        2. 2.5.2.2 Clock Configuration
        3. 2.5.2.3 IEP Timer Configuration
        4. 2.5.2.4 TSR Configuration
        5. 2.5.2.5 Task Manager Configuration
  6. 3Verification
  7. 4Summary
  8. 5References

3 Verification

To verify the scheme, 2 AM243x launch Pad are used with some hardware connection including:

  • Connect LP-AM243x device 1 BP.45 (SYNCOUT0) to LP-AM243x device 2 BP.8 (LATCH_IN0) by wire
  • Connect device 1 J16 pin 1 (FSI RXCLK) to device 2 J16 pin 2 (FSI TXCLK) by wire
  • Connect device 1 J16 pin 5 (FSI RXD0) to device 2 J16 pin 6 (FSI TXD0) by wire
  • Connect device 1 J16 pin 7 (FSI RXD1) to device 2 J16 pin 8 (FSI TXD1) by wire
  • Connect device 1 J16 pin 3 (GND) to device 2 J16 pin 4 (GND) by wire

Figure 3-1 shows the verification set up for the demo and Figure 3-2 is the waveform for the timing of all the signals including:

  • Channel 0: device 2 – BP.33 (PRG0_PRU0_GPO0 toggling to show the cycle time using IEP compare0 event)
  • Channel 1: device 2 – BP.32 (PRG0_PRU0_GPO1 toggling to show the task 2 triggered by IEP compare2 event used for pre-scheduled starting time of position sense)
  • Channel 2: device 2 – BP.31 (PRG0_PRU0_GPO2 toggling to show the task 3 triggered by IEP compare3 event used for pre-scheduled starting time of position data transmitting via FSI)
  • Channel 3: device 1 – J6 pin1 (FSI TX CLK) or device 2 – J16 pin 2 (FSI RX CLK)
  • Channel 4: device 1 – BP.11 (PRG0_PRU1_GPO0 toggling to show the task 1 triggered by INTC event used for move the position data from FSI RX buffer to TCM)
  • Channel 5: device 1 – BP.51 (system GPO1_20 toggling to show PRU1 interrupt once the position data movement finished)
  • Channel 6: device 1 – BP.45 (IEP0_SYNCOUT0)
  • Channel 7: device 2 – BP.45 (IEP0_SYNCOUT0)
Verification Demo Set UpFigure 3-1 Verification Demo Set Up
Overall Timing of all SignalingFigure 3-2 Overall Timing of all Signaling

The cycle time is set to 62.5us at the PWM cycle level (16kHz) which shows on channel 0. The position sense starts at the central point of the cycle which shows on channel 1. The FSI latency including the processing time for FSI TX and RX also the data transmitting is shown on channel 2, channel 4 and channel 3 respectively. The total communication latency via FSI is around 3.046us for transmitting 32 bytes data words. Channel 6 and 7 are the IEP SYNCOUT0 signals generated by both device 1 and device 2 which are aligned well by compensate the delay. Figure 3-3 shows the verification results mentioned above. Also Figure 3-4 shows the drift of IEP SYNCOUT0 pulse between device 1 and device 2 is less than 5ns with overnight testing. The drift is compensated in the device 2. Thus, the process synchronize the IEP counters of two AM243x devices.

Verification Results of the TimingFigure 3-3 Verification Results of the Timing
Overnight Testing Result for Drift of IEP SYNCOUT0 Between DevicesFigure 3-4 Overnight Testing Result for Drift of IEP SYNCOUT0 Between Devices

The data transmitting validation result is shown on Figure 3-5. 32 bytes data are written into the ICSSG Dynamic Random-Access Memory (DRAM) of device 2 in advance as the position data. Tightly Coupled Memory (TCM) of device 1 stores the data received from FSI RX buffer. All the data is copied to the debug buffer gRxBufData inside the PRU core interrupt to showcase the data validation.

Data Transmitting Validation ResultFigure 3-5 Data Transmitting Validation Result